{"id":"https://openalex.org/W2141115460","doi":"https://doi.org/10.1109/dftvs.2002.1173519","title":"A memory overhead evaluation of the interleaved signature instruction stream","display_name":"A memory overhead evaluation of the interleaved signature instruction stream","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2141115460","doi":"https://doi.org/10.1109/dftvs.2002.1173519","mag":"2141115460"},"language":"en","primary_location":{"id":"doi:10.1109/dftvs.2002.1173519","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2002.1173519","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101809212","display_name":"Francisco Rodr\u00edguez\u2010Ballester","orcid":"https://orcid.org/0000-0002-4087-5077"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"F. Rodriguez","raw_affiliation_strings":["Grupo de Sistemas Tolerantes a Fallos-Fault Tolerant Systems GroupDepartment Inform\u00e1tica de Sistemas y Computadores, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain","Dept. de Sistemas Inf. y Comput., Univ. Politecnica de Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Grupo de Sistemas Tolerantes a Fallos-Fault Tolerant Systems GroupDepartment Inform\u00e1tica de Sistemas y Computadores, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Dept. de Sistemas Inf. y Comput., Univ. Politecnica de Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087867274","display_name":"J.C. Campelo","orcid":"https://orcid.org/0000-0003-0558-7683"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J.C. Campelo","raw_affiliation_strings":["Grupo de Sistemas Tolerantes a Fallos-Fault Tolerant Systems GroupDepartment Inform\u00e1tica de Sistemas y Computadores, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain","Dept. de Sistemas Inf. y Comput., Univ. Politecnica de Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Grupo de Sistemas Tolerantes a Fallos-Fault Tolerant Systems GroupDepartment Inform\u00e1tica de Sistemas y Computadores, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Dept. de Sistemas Inf. y Comput., Univ. Politecnica de Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103576150","display_name":"J.J. Serrano","orcid":null},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J.J. Serrano","raw_affiliation_strings":["Grupo de Sistemas Tolerantes a Fallos-Fault Tolerant Systems GroupDepartment Inform\u00e1tica de Sistemas y Computadores, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain","Dept. de Sistemas Inf. y Comput., Univ. Politecnica de Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Grupo de Sistemas Tolerantes a Fallos-Fault Tolerant Systems GroupDepartment Inform\u00e1tica de Sistemas y Computadores, Universidad Polit\u00e9cnica de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Dept. de Sistemas Inf. y Comput., Univ. Politecnica de Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101809212"],"corresponding_institution_ids":["https://openalex.org/I60053951"],"apc_list":null,"apc_paid":null,"fwci":0.6955,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.73580891,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"225","last_page":"232"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8270412087440491},{"id":"https://openalex.org/keywords/memory-protection","display_name":"Memory protection","score":0.6140739917755127},{"id":"https://openalex.org/keywords/dependability","display_name":"Dependability","score":0.6053767204284668},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5368168354034424},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.526877224445343},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5230525732040405},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.500399112701416},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.478342741727829},{"id":"https://openalex.org/keywords/signature","display_name":"Signature (topology)","score":0.47694769501686096},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4621674716472626},{"id":"https://openalex.org/keywords/stream-processing","display_name":"Stream processing","score":0.41673150658607483},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.41605108976364136},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3296589255332947},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.28424179553985596},{"id":"https://openalex.org/keywords/virtual-memory","display_name":"Virtual memory","score":0.20520752668380737},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18531188368797302},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.1830633580684662},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.11219584941864014}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8270412087440491},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.6140739917755127},{"id":"https://openalex.org/C77019957","wikidata":"https://www.wikidata.org/wiki/Q2689057","display_name":"Dependability","level":2,"score":0.6053767204284668},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5368168354034424},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.526877224445343},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5230525732040405},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.500399112701416},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.478342741727829},{"id":"https://openalex.org/C2779696439","wikidata":"https://www.wikidata.org/wiki/Q7512811","display_name":"Signature (topology)","level":2,"score":0.47694769501686096},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4621674716472626},{"id":"https://openalex.org/C107027933","wikidata":"https://www.wikidata.org/wiki/Q2006448","display_name":"Stream processing","level":2,"score":0.41673150658607483},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.41605108976364136},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3296589255332947},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.28424179553985596},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.20520752668380737},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18531188368797302},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.1830633580684662},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.11219584941864014},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dftvs.2002.1173519","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2002.1173519","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320324278","display_name":"Comisi\u00f3n Interministerial de Ciencia y Tecnolog\u00eda","ror":"https://ror.org/034900433"},{"id":"https://openalex.org/F4320330412","display_name":"Scheme for Promotion of Academic and Research Collaboration","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W132647800","https://openalex.org/W1543978957","https://openalex.org/W1547528813","https://openalex.org/W1547613762","https://openalex.org/W1897867350","https://openalex.org/W1981514768","https://openalex.org/W2046626970","https://openalex.org/W2103769510","https://openalex.org/W2139416948","https://openalex.org/W2139570402","https://openalex.org/W4285719527","https://openalex.org/W6605400777","https://openalex.org/W7065805605"],"related_works":["https://openalex.org/W4200599950","https://openalex.org/W4317937473","https://openalex.org/W4386213660","https://openalex.org/W4383333855","https://openalex.org/W4296991050","https://openalex.org/W2026197855","https://openalex.org/W2147318068","https://openalex.org/W2993622674","https://openalex.org/W2176283981","https://openalex.org/W3116750762"],"abstract_inverted_index":{"Using":[0],"a":[1,9,14,22,53,68,88],"watchdog":[2,32,113],"processor":[3,10,33,36,72,91,114],"for":[4,30],"concurrent":[5],"error":[6,76],"detection":[7,77],"of":[8,21,109,118],"execution":[11],"flow":[12],"is":[13,52],"well-known":[15],"technique":[16,51,56,82],"to":[17,60],"increase":[18],"the":[19,31,35,63,98,106,132],"dependability":[20],"microprocessor":[23],"system.":[24],"Most":[25],"approaches":[26],"embed":[27],"reference":[28],"signatures":[29,59],"into":[34,86],"instruction":[37,48,65],"stream":[38,49,66],"creating":[39],"noticeable":[40],"memory":[41,120],"and":[42,115],"performance":[43,107],"overheads.":[44],"The":[45],"interleaved":[46],"signature":[47,54],"(ISIS)":[50],"embedding":[55],"that":[57],"allows":[58],"co-exist":[61],"with":[62,67],"main":[64],"minimal":[69],"impact":[70,108],"on":[71],"performance,":[73],"without":[74],"sacrificing":[75],"coverage":[78],"or":[79],"latency.":[80],"This":[81,95],"has":[83],"been":[84],"implemented":[85],"HORUS,":[87],"MIPS-like":[89],"RISC":[90],"developed":[92],"in":[93,131],"VHDL.":[94],"paper":[96],"presents":[97],"HORUS":[99],"architecture":[100],"novelties":[101],"demanded":[102],"by":[103],"ISIS,":[104],"discusses":[105],"adding":[110],"an":[111],"ISIS":[112,119],"provides":[116],"results":[117,123],"overhead.":[121],"These":[122],"are":[124],"compared":[125],"against":[126],"similar":[127],"solutions":[128],"previously":[129],"presented":[130],"literature.":[133]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}