{"id":"https://openalex.org/W2132926402","doi":"https://doi.org/10.1109/dftvs.2002.1173516","title":"Testing digital circuits with constraints","display_name":"Testing digital circuits with constraints","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2132926402","doi":"https://doi.org/10.1109/dftvs.2002.1173516","mag":"2132926402"},"language":"en","primary_location":{"id":"doi:10.1109/dftvs.2002.1173516","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2002.1173516","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110097697","display_name":"A.A. Al-Yamani","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A.A. Al-Yamani","raw_affiliation_strings":["Center for Reliable Computing, University of Stanford, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Center for Reliable Computing, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036312663","display_name":"Subhasish Mitra","orcid":"https://orcid.org/0000-0002-5572-5194"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Mitra","raw_affiliation_strings":["Intel Corporation, Sacramento, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Sacramento, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054077540","display_name":"E.J. McCluskey","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E.J. McCluskey","raw_affiliation_strings":["Center for Reliable Computing, University of Stanford, Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Center for Reliable Computing, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110097697"],"corresponding_institution_ids":["https://openalex.org/I97018004"],"apc_list":null,"apc_paid":null,"fwci":1.0062,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.77759377,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"195","last_page":"203"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.7772536277770996},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.7161312103271484},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.652518630027771},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5978362560272217},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5738484263420105},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.5467504262924194},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5283694267272949},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.513990581035614},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.48040154576301575},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4799504578113556},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.4364885687828064},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.43292009830474854},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4044472575187683},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3610525131225586},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2488017976284027},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21667447686195374},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08101505041122437},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08020246028900146}],"concepts":[{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.7772536277770996},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.7161312103271484},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.652518630027771},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5978362560272217},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5738484263420105},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.5467504262924194},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5283694267272949},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.513990581035614},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.48040154576301575},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4799504578113556},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.4364885687828064},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.43292009830474854},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4044472575187683},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3610525131225586},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2488017976284027},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21667447686195374},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08101505041122437},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08020246028900146},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dftvs.2002.1173516","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2002.1173516","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7900000214576721,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W615030097","https://openalex.org/W1604154703","https://openalex.org/W1773293510","https://openalex.org/W1874075800","https://openalex.org/W1902443706","https://openalex.org/W1905213452","https://openalex.org/W1944607425","https://openalex.org/W2109678242","https://openalex.org/W2132926402","https://openalex.org/W2148357511","https://openalex.org/W2154811899","https://openalex.org/W2165157401","https://openalex.org/W2283481854","https://openalex.org/W2888938350"],"related_works":["https://openalex.org/W2117563988","https://openalex.org/W2091833418","https://openalex.org/W1412895167","https://openalex.org/W2120257283","https://openalex.org/W2913077774","https://openalex.org/W4256030018","https://openalex.org/W1493811107","https://openalex.org/W2154529098","https://openalex.org/W2109319621","https://openalex.org/W2015972826"],"abstract_inverted_index":{"Many":[0],"digital":[1,33],"circuits":[2,34],"have":[3],"constraints":[4],"on":[5],"the":[6,26,43,47,67,80,84],"logic":[7,30],"values":[8,31],"a":[9,89],"set":[10,92],"of":[11,29,53,70,83],"signal":[12],"lines":[13],"can":[14],"have.":[15],"In":[16],"this":[17],"paper,":[18],"we":[19],"present":[20],"two":[21,36],"new":[22],"techniques":[23,37,72,101],"for":[24,38],"detecting":[25],"illegal":[27],"combinations":[28],"in":[32,88],"and":[35,58,111],"preventing":[39],"them":[40],"from":[41],"damaging":[42],"circuit":[44],"or":[45],"corrupting":[46],"test":[48,86,91],"results.":[49],"The":[50],"hardware":[51],"overhead":[52,69],"our":[54,71,97,100],"technique":[55],"is":[56,73,93],"minimal":[57],"imposes":[59],"negligible":[60],"delay":[61],"overhead.":[62],"Simulation":[63],"results":[64],"show":[65],"that":[66],"area":[68],"less":[74],"than":[75],"1%.":[76],"Unlike":[77],"previous":[78],"techniques,":[79],"fault":[81],"coverage":[82],"legal":[85],"patterns":[87],"given":[90],"not":[94],"sacrificed":[95],"with":[96],"techniques.":[98],"Furthermore,":[99],"are":[102],"applicable":[103],"during":[104],"IC":[105],"production":[106],"test,":[107],"BIST,":[108],"board-level":[109],"tests":[110],"system-level":[112],"tests.":[113]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
