{"id":"https://openalex.org/W2147584640","doi":"https://doi.org/10.1109/dftvs.2002.1173496","title":"Manufacturability analysis of analog CMOS ICs through examination of multiple layout solutions","display_name":"Manufacturability analysis of analog CMOS ICs through examination of multiple layout solutions","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2147584640","doi":"https://doi.org/10.1109/dftvs.2002.1173496","mag":"2147584640"},"language":"en","primary_location":{"id":"doi:10.1109/dftvs.2002.1173496","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2002.1173496","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019415739","display_name":"P. Khademsameni","orcid":null},"institutions":[{"id":"https://openalex.org/I18014758","display_name":"Simon Fraser University","ror":"https://ror.org/0213rcc28","country_code":"CA","type":"education","lineage":["https://openalex.org/I18014758"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"P. Khademsameni","raw_affiliation_strings":["School of Engineering Science, Simon Fraser University, BC, Canada"],"affiliations":[{"raw_affiliation_string":"School of Engineering Science, Simon Fraser University, BC, Canada","institution_ids":["https://openalex.org/I18014758"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039167594","display_name":"M. Syrzycki","orcid":null},"institutions":[{"id":"https://openalex.org/I18014758","display_name":"Simon Fraser University","ror":"https://ror.org/0213rcc28","country_code":"CA","type":"education","lineage":["https://openalex.org/I18014758"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Syrzycki","raw_affiliation_strings":["School of Engineering Science, Simon Fraser University, BC, Canada"],"affiliations":[{"raw_affiliation_string":"School of Engineering Science, Simon Fraser University, BC, Canada","institution_ids":["https://openalex.org/I18014758"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5019415739"],"corresponding_institution_ids":["https://openalex.org/I18014758"],"apc_list":null,"apc_paid":null,"fwci":0.3477,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.65473828,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"26","issue":null,"first_page":"3","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.9793624877929688},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7452589273452759},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.7303144931793213},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.6685240268707275},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.661695122718811},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5393412709236145},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5096497535705566},{"id":"https://openalex.org/keywords/design-layout-record","display_name":"Design layout record","score":0.4863949120044708},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47207000851631165},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.45223870873451233},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.428928941488266},{"id":"https://openalex.org/keywords/technology-cad","display_name":"Technology CAD","score":0.42835694551467896},{"id":"https://openalex.org/keywords/semiconductor-device-modeling","display_name":"Semiconductor device modeling","score":0.416908860206604},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4061747193336487},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.38398054242134094},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.37773948907852173},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.3266906440258026},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.27940261363983154},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13160225749015808},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.0956626832485199}],"concepts":[{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.9793624877929688},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7452589273452759},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.7303144931793213},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.6685240268707275},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.661695122718811},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5393412709236145},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5096497535705566},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.4863949120044708},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47207000851631165},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.45223870873451233},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.428928941488266},{"id":"https://openalex.org/C34929307","wikidata":"https://www.wikidata.org/wiki/Q845636","display_name":"Technology CAD","level":3,"score":0.42835694551467896},{"id":"https://openalex.org/C4775677","wikidata":"https://www.wikidata.org/wiki/Q7449393","display_name":"Semiconductor device modeling","level":3,"score":0.416908860206604},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4061747193336487},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.38398054242134094},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.37773948907852173},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.3266906440258026},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.27940261363983154},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13160225749015808},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.0956626832485199},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dftvs.2002.1173496","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dftvs.2002.1173496","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1496970834","https://openalex.org/W1582472333","https://openalex.org/W1986941465","https://openalex.org/W2037926253","https://openalex.org/W2041090186","https://openalex.org/W2129555080","https://openalex.org/W2131973905","https://openalex.org/W2155220114","https://openalex.org/W3116648946","https://openalex.org/W6787885146"],"related_works":["https://openalex.org/W2091329789","https://openalex.org/W2595178692","https://openalex.org/W1873584906","https://openalex.org/W2044122268","https://openalex.org/W2003092850","https://openalex.org/W2248366743","https://openalex.org/W1605062719","https://openalex.org/W2376028644","https://openalex.org/W2357425846","https://openalex.org/W2123992435"],"abstract_inverted_index":{"Introduces":[0],"a":[1,22,31,92],"methodology":[2,12],"for":[3,38,79,102],"the":[4,45,51,77],"manufacturability":[5,109],"analysis":[6,106],"of":[7,17,21,72,98,107],"analog":[8],"CMOS":[9],"ICs.":[10],"The":[11,64,81,96],"is":[13,36,85],"based":[14],"on":[15],"examination":[16],"several":[18],"layout":[19,40,47,103],"solutions":[20],"single":[23],"circuit.":[24],"A":[25],"critical":[26],"area":[27],"approach":[28],"to":[29],"evaluate":[30],"theoretical":[32,52,65],"random-defect":[33],"limited":[34],"yield":[35,53,66],"applied":[37],"each":[39],"solution.":[41],"Users":[42],"can":[43],"choose":[44],"appropriate":[46],"solution":[48],"after":[49],"comparing":[50],"values":[54],"and":[55,105],"considering":[56],"results":[57],"obtained":[58],"from":[59],"economical":[60],"post-layout":[61],"simulation":[62],"tools.":[63],"has":[67,88],"been":[68,89],"proposed":[69],"as":[70],"one":[71],"possible":[73],"quality":[74],"factors":[75],"in":[76,91],"design":[78],"manufacturability.":[80],"multi-layout":[82],"approach,":[83],"which":[84],"presented":[86,112],"here,":[87],"implemented":[90],"CAD":[93,100],"tool":[94,101],"(ALDAC).":[95],"use":[97],"this":[99],"generation":[104],"circuit":[108],"will":[110],"be":[111],"here.":[113]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}