{"id":"https://openalex.org/W4416725598","doi":"https://doi.org/10.1109/dft66274.2025.11257546","title":"Optimizing Software Self-Test Pattern Generation for Specific Components","display_name":"Optimizing Software Self-Test Pattern Generation for Specific Components","publication_year":2025,"publication_date":"2025-10-21","ids":{"openalex":"https://openalex.org/W4416725598","doi":"https://doi.org/10.1109/dft66274.2025.11257546"},"language":null,"primary_location":{"id":"doi:10.1109/dft66274.2025.11257546","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft66274.2025.11257546","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5098660662","display_name":"Jad Al Halabi","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Jad Al Halabi","raw_affiliation_strings":["Infineon Technologies AG,Munich,Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG,Munich,Germany","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5120616674","display_name":"Melis Cetinkaya","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Melis Cetinkaya","raw_affiliation_strings":["Infineon Technologies AG,Munich,Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG,Munich,Germany","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013456037","display_name":"Endri Kaja","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Endri Kaja","raw_affiliation_strings":["Infineon Technologies AG,Munich,Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG,Munich,Germany","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022028075","display_name":"Mounika Vaddeboina","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Mounika Vaddeboina","raw_affiliation_strings":["Infineon Technologies AG,Munich,Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG,Munich,Germany","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046956677","display_name":"Wolfgang Ecker","orcid":"https://orcid.org/0000-0002-9362-8096"},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfgang Ecker","raw_affiliation_strings":["Infineon Technologies AG,Munich,Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG,Munich,Germany","institution_ids":["https://openalex.org/I137594350"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5098660662"],"corresponding_institution_ids":["https://openalex.org/I137594350"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.42420057,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9656000137329102,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9656000137329102,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.009399999864399433,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.0044999998062849045,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5410000085830688},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.49950000643730164},{"id":"https://openalex.org/keywords/miniaturization","display_name":"Miniaturization","score":0.4966999888420105},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.48500001430511475},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.48010000586509705},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.43950000405311584},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.4374000132083893},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.43059998750686646},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4235000014305115},{"id":"https://openalex.org/keywords/fault-model","display_name":"Fault model","score":0.4011000096797943}],"concepts":[{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5410000085830688},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.49950000643730164},{"id":"https://openalex.org/C57528182","wikidata":"https://www.wikidata.org/wiki/Q1271842","display_name":"Miniaturization","level":2,"score":0.4966999888420105},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.48500001430511475},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.48010000586509705},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4406999945640564},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.43950000405311584},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.4374000132083893},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.43059998750686646},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4253999888896942},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4235000014305115},{"id":"https://openalex.org/C167391956","wikidata":"https://www.wikidata.org/wiki/Q1401211","display_name":"Fault model","level":3,"score":0.4011000096797943},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.38359999656677246},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3682999908924103},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3643999993801117},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.35929998755455017},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.3553999960422516},{"id":"https://openalex.org/C2776365744","wikidata":"https://www.wikidata.org/wiki/Q5438149","display_name":"Fault Simulator","level":5,"score":0.3481000065803528},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.33489999175071716},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.3343000113964081},{"id":"https://openalex.org/C107551265","wikidata":"https://www.wikidata.org/wiki/Q1458245","display_name":"Displacement (psychology)","level":2,"score":0.3294999897480011},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.32420000433921814},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32350000739097595},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.3231000006198883},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.32179999351501465},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.3199999928474426},{"id":"https://openalex.org/C81060104","wikidata":"https://www.wikidata.org/wiki/Q11653","display_name":"Electronic component","level":2,"score":0.31060001254081726},{"id":"https://openalex.org/C2779662365","wikidata":"https://www.wikidata.org/wiki/Q5416694","display_name":"Event (particle physics)","level":2,"score":0.3102000057697296},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.30880001187324524},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.30880001187324524},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.30070000886917114},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.2987000048160553},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.29319998621940613},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.28630000352859497},{"id":"https://openalex.org/C50712370","wikidata":"https://www.wikidata.org/wiki/Q4269346","display_name":"Software fault tolerance","level":3,"score":0.2809000015258789},{"id":"https://openalex.org/C141400236","wikidata":"https://www.wikidata.org/wiki/Q1479544","display_name":"Nanoelectronics","level":2,"score":0.2777999937534332},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.2646999955177307},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.2621000111103058},{"id":"https://openalex.org/C165862026","wikidata":"https://www.wikidata.org/wiki/Q670372","display_name":"NOR logic","level":5,"score":0.25130000710487366}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dft66274.2025.11257546","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft66274.2025.11257546","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1891950198","https://openalex.org/W2037073597","https://openalex.org/W2162696040","https://openalex.org/W2550854960","https://openalex.org/W3140566188","https://openalex.org/W3210162968","https://openalex.org/W4230017220","https://openalex.org/W4310502075","https://openalex.org/W4404564603"],"related_works":[],"abstract_inverted_index":{"The":[0,166,184],"continuous":[1],"drive":[2],"toward":[3],"the":[4,12,42,52,126,171,197],"miniaturization":[5],"of":[6,15,54,111,170,190,192],"Integrated":[7],"Circuits":[8],"(ICs)":[9],"is":[10,107,116],"pushing":[11],"physical":[13],"boundaries":[14],"device":[16],"scaling.":[17],"As":[18],"transistor":[19],"gate":[20],"and":[21,35,71,98,113,174,176],"interconnect":[22],"dimensions":[23],"shrink,":[24],"several":[25],"challenges":[26],"emerge,":[27],"including":[28],"increased":[29],"power":[30],"density,":[31],"thermal":[32],"dissipation":[33],"constraints,":[34],"quantum":[36],"effects.":[37],"Among":[38],"these,":[39],"electromigration\u2014caused":[40],"by":[41],"momentum":[43],"transfer":[44],"from":[45],"high":[46,134],"current":[47],"densities":[48],"to":[49,60,124,180],"atoms\u2014results":[50],"in":[51,109,196],"displacement":[53],"material":[55],"within":[56],"interconnects,":[57],"potentially":[58],"leading":[59],"unintended":[61],"open":[62],"circuits":[63],"or":[64,88],"shorts.":[65],"Similarly,":[66],"manufacturing":[67],"defects,":[68],"environmental":[69],"stresses,":[70],"aging":[72],"effects":[73],"further":[74],"exacerbate":[75],"these":[76,93],"reliability":[77],"issues,":[78,94],"often":[79],"manifesting":[80],"as":[81,85,161],"permanent":[82],"faults,":[83],"such":[84,160],"logic":[86],"stuck-at-0":[87],"stuck-at-1":[89],"conditions.":[90],"To":[91],"address":[92],"Design-for-Test":[95],"(DFT)":[96],"infrastructure":[97],"Software-Based":[99],"Self-Test":[100],"(SBST)":[101],"have":[102],"been":[103],"developed.":[104],"While":[105],"DFT":[106],"expensive":[108],"terms":[110],"area":[112],"performance,":[114],"SBST":[115,152],"a":[117,138,145,162,187],"cost-effective":[118],"alternative":[119],"that":[120],"uses":[121,177],"processor":[122],"resources":[123],"test":[125,131],"chip.":[127],"However,":[128],"generating":[129],"efficient":[130],"patterns":[132],"with":[133,157],"fault":[135,178,182,188],"coverage":[136,189],"remains":[137],"challenge.":[139],"In":[140],"this":[141],"paper,":[142],"we":[143],"propose":[144],"technique":[146],"for":[147,151],"optimizing":[148],"testing":[149],"software":[150],"targeted":[153],"towards":[154],"specific":[155],"components":[156],"uniform":[158],"structures":[159],"RISC-V":[163],"Register":[164,198],"File.":[165,199],"method":[167,185],"requires":[168],"knowledge":[169],"component":[172],"structure":[173],"function,":[175],"simulation":[179],"verify":[181],"coverage.":[183],"achieved":[186],"99%":[191],"functionally":[193],"testable":[194],"faults":[195]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-11-25T00:00:00"}
