{"id":"https://openalex.org/W4416726308","doi":"https://doi.org/10.1109/dft66274.2025.11257459","title":"Reliability and Performance Evaluation of a Fault-Tolerant MPSoC Interconnection Architecture","display_name":"Reliability and Performance Evaluation of a Fault-Tolerant MPSoC Interconnection Architecture","publication_year":2025,"publication_date":"2025-10-21","ids":{"openalex":"https://openalex.org/W4416726308","doi":"https://doi.org/10.1109/dft66274.2025.11257459"},"language":null,"primary_location":{"id":"doi:10.1109/dft66274.2025.11257459","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft66274.2025.11257459","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108939303","display_name":"Thiago H. Rausch","orcid":null},"institutions":[{"id":"https://openalex.org/I4210144729","display_name":"Universidade do Vale do Itaja\u00ed","ror":"https://ror.org/041pjwa23","country_code":"BR","type":"education","lineage":["https://openalex.org/I4210144729"]},{"id":"https://openalex.org/I165476936","display_name":"Vale (Brazil)","ror":"https://ror.org/05a99n355","country_code":"BR","type":"company","lineage":["https://openalex.org/I165476936"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Thiago H. Rausch","raw_affiliation_strings":["LEDS, University of Vale do Itajaí,Brazil"],"affiliations":[{"raw_affiliation_string":"LEDS, University of Vale do Itajaí,Brazil","institution_ids":["https://openalex.org/I4210144729","https://openalex.org/I165476936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016727541","display_name":"Wesley Grignani","orcid":"https://orcid.org/0000-0003-4865-9333"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Wesley Grignani","raw_affiliation_strings":["IES, University of Montpellier, CNRS,Montpellier,France"],"affiliations":[{"raw_affiliation_string":"IES, University of Montpellier, CNRS,Montpellier,France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001777299","display_name":"Luigi Dilillo","orcid":"https://orcid.org/0000-0002-1295-2688"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Luigi Dilillo","raw_affiliation_strings":["IES, University of Montpellier, CNRS,Montpellier,France"],"affiliations":[{"raw_affiliation_string":"IES, University of Montpellier, CNRS,Montpellier,France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I1294671590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007786013","display_name":"Douglas R. Melo","orcid":"https://orcid.org/0000-0001-5791-6958"},"institutions":[{"id":"https://openalex.org/I165476936","display_name":"Vale (Brazil)","ror":"https://ror.org/05a99n355","country_code":"BR","type":"company","lineage":["https://openalex.org/I165476936"]},{"id":"https://openalex.org/I4210144729","display_name":"Universidade do Vale do Itaja\u00ed","ror":"https://ror.org/041pjwa23","country_code":"BR","type":"education","lineage":["https://openalex.org/I4210144729"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Douglas R. Melo","raw_affiliation_strings":["LEDS, University of Vale do Itajaí,Brazil"],"affiliations":[{"raw_affiliation_string":"LEDS, University of Vale do Itajaí,Brazil","institution_ids":["https://openalex.org/I4210144729","https://openalex.org/I165476936"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5108939303"],"corresponding_institution_ids":["https://openalex.org/I165476936","https://openalex.org/I4210144729"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.44169019,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9161999821662903,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9161999821662903,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.03629999980330467,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12449","display_name":"Spacecraft Design and Technology","score":0.01549999974668026,"subfield":{"id":"https://openalex.org/subfields/2202","display_name":"Aerospace Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8119000196456909},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.7157999873161316},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6521999835968018},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6359999775886536},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5149000287055969},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.4945000112056732},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.44440001249313354},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.44119998812675476},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.39899998903274536}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8119000196456909},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.7157999873161316},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6521999835968018},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6359999775886536},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.635699987411499},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.595300018787384},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5149000287055969},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4945000112056732},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.44440001249313354},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.44119998812675476},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.39899998903274536},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3935999870300293},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.3917999863624573},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.37860000133514404},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.3425000011920929},{"id":"https://openalex.org/C73150493","wikidata":"https://www.wikidata.org/wiki/Q853922","display_name":"Hamming code","level":4,"score":0.3174999952316284},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3077000081539154},{"id":"https://openalex.org/C193415008","wikidata":"https://www.wikidata.org/wiki/Q639681","display_name":"Network architecture","level":2,"score":0.3005000054836273},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.3001999855041504},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.2989000082015991},{"id":"https://openalex.org/C32833848","wikidata":"https://www.wikidata.org/wiki/Q4115054","display_name":"Extensibility","level":2,"score":0.2833000123500824},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2799000144004822},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.2799000144004822},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.27549999952316284},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.272599995136261},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.2712000012397766},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.2596000134944916},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.2554999887943268}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dft66274.2025.11257459","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft66274.2025.11257459","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1580327099","https://openalex.org/W2408761616","https://openalex.org/W2981662491","https://openalex.org/W2993515149","https://openalex.org/W3087455367","https://openalex.org/W3185282005","https://openalex.org/W4229597501","https://openalex.org/W4399324116","https://openalex.org/W4403048326","https://openalex.org/W4407393882"],"related_works":[],"abstract_inverted_index":{"The":[0],"increasing":[1],"adoption":[2],"of":[3,25,68,140,159],"Multiprocessor":[4],"System-on-Chip":[5],"(MPSoC)":[6],"architectures":[7],"in":[8,143],"space":[9],"applications":[10],"demands":[11],"highly":[12],"reliable":[13,47],"interconnection":[14],"solutions":[15],"resilient":[16],"to":[17,45,64,92],"radiation-induced":[18],"faults.":[19],"This":[20],"paper":[21],"evaluates":[22],"the":[23,26,66,100,106,133,144,149,157],"reliability":[24],"eXtensible":[27],"Interconnect":[28],"Network":[29,40],"Architecture":[30],"(XINA),":[31],"a":[32,37,86,93,136],"fault-tolerant":[33],"Network-on-Chip":[34],"(NoC)":[35],"featuring":[36],"robust,":[38],"AXI-compatible":[39],"Interface":[41],"(NI),":[42],"specifically":[43],"designed":[44],"maintain":[46],"communication":[48],"under":[49],"harsh":[50],"environmental":[51],"conditions.":[52],"XINA":[53],"incorporates":[54],"Triple":[55],"Modular":[56],"Redundancy":[57],"(TMR)":[58],"and":[59,72,108,111,119,163],"Hamming":[60],"Error-Correcting":[61],"Codes":[62],"(ECC)":[63],"enhance":[65],"robustness":[67],"both":[69,105],"NoC":[70,107],"routers":[71],"NI":[73],"components,":[74],"while":[75,148],"remaining":[76],"fully":[77,150],"compatible":[78],"with":[79],"standard":[80],"AMBA":[81],"AXI":[82],"IP":[83],"cores.":[84],"Using":[85],"simulation-based":[87],"fault":[88,101],"injection":[89],"methodology":[90],"applied":[91],"large-scale":[94],"100-core":[95],"MPSoC":[96],"implementation,":[97],"we":[98],"quantify":[99],"tolerance":[102],"provided":[103],"by":[104],"its":[109],"NI,":[110],"analyze":[112],"their":[113],"combined":[114],"impact":[115],"on":[116],"performance,":[117],"area,":[118],"power":[120],"consumption.":[121],"Four":[122],"design":[123],"variants":[124],"combining":[125],"different":[126],"protection":[127],"levels":[128],"were":[129],"evaluated.":[130],"Results":[131],"demonstrate":[132],"system":[134],"sustained":[135],"peak":[137],"global":[138],"throughput":[139],"2.12":[141],"Gbps":[142],"unprotected":[145],"baseline":[146],"configuration,":[147],"protected":[151],"configuration":[152],"reduced":[153,164],"error":[154],"occurrences":[155],"at":[156],"cost":[158],"increased":[160],"resource":[161],"utilization":[162],"operating":[165],"frequency.":[166]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-11-25T00:00:00"}