{"id":"https://openalex.org/W4388667102","doi":"https://doi.org/10.1109/dft59622.2023.10313533","title":"Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis","display_name":"Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis","publication_year":2023,"publication_date":"2023-10-03","ids":{"openalex":"https://openalex.org/W4388667102","doi":"https://doi.org/10.1109/dft59622.2023.10313533"},"language":"en","primary_location":{"id":"doi:10.1109/dft59622.2023.10313533","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft59622.2023.10313533","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015586753","display_name":"Christos Georgakidis","orcid":"https://orcid.org/0000-0002-7491-2606"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Christos Georgakidis","raw_affiliation_strings":["University of Thessaly,Department of Electrical and Computer Engineering,Greece","Department of Electrical and Computer Engineering, University of Thessaly, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly,Department of Electrical and Computer Engineering,Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013089903","display_name":"Dimitris Valiantzas","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Dimitris Valiantzas","raw_affiliation_strings":["University of Thessaly,Department of Electrical and Computer Engineering,Greece","Department of Electrical and Computer Engineering, University of Thessaly, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly,Department of Electrical and Computer Engineering,Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057901469","display_name":"Stavros Simoglou","orcid":"https://orcid.org/0000-0003-0015-7510"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Stavros Simoglou","raw_affiliation_strings":["University of Thessaly,Department of Electrical and Computer Engineering,Greece","Department of Electrical and Computer Engineering, University of Thessaly, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly,Department of Electrical and Computer Engineering,Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035300872","display_name":"Iordanis Lilitsis","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Iordanis Lilitsis","raw_affiliation_strings":["University of Thessaly,Department of Electrical and Computer Engineering,Greece","Department of Electrical and Computer Engineering, University of Thessaly, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly,Department of Electrical and Computer Engineering,Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057971669","display_name":"Nikolaos Chatzivangelis","orcid":"https://orcid.org/0009-0008-1050-046X"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Nikolaos Chatzivangelis","raw_affiliation_strings":["University of Thessaly,Department of Electrical and Computer Engineering,Greece","Department of Electrical and Computer Engineering, University of Thessaly, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly,Department of Electrical and Computer Engineering,Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093260778","display_name":"Ilias Golfos","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Ilias Golfos","raw_affiliation_strings":["University of Thessaly,Department of Electrical and Computer Engineering,Greece","Department of Electrical and Computer Engineering, University of Thessaly, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly,Department of Electrical and Computer Engineering,Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039322577","display_name":"Marko Andjelkovi\u0107","orcid":"https://orcid.org/0000-0001-6419-2062"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Marko Andjelkovic","raw_affiliation_strings":["IHP - Leibniz Institut f&#x00FC;r Innovative Mikroelektronik,Germany"],"affiliations":[{"raw_affiliation_string":"IHP - Leibniz Institut f&#x00FC;r Innovative Mikroelektronik,Germany","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103066371","display_name":"Christos Sotiriou","orcid":"https://orcid.org/0000-0001-9318-474X"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Christos Sotiriou","raw_affiliation_strings":["University of Thessaly,Department of Electrical and Computer Engineering,Greece","Department of Electrical and Computer Engineering, University of Thessaly, Greece"],"affiliations":[{"raw_affiliation_string":"University of Thessaly,Department of Electrical and Computer Engineering,Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Thessaly, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004959402","display_name":"Milo\u0161 Krsti\u0107","orcid":"https://orcid.org/0000-0003-0267-0203"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Milos Krstic","raw_affiliation_strings":["IHP - Leibniz Institut f&#x00FC;r Innovative Mikroelektronik,Germany"],"affiliations":[{"raw_affiliation_string":"IHP - Leibniz Institut f&#x00FC;r Innovative Mikroelektronik,Germany","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5015586753"],"corresponding_institution_ids":["https://openalex.org/I145722265"],"apc_list":null,"apc_paid":null,"fwci":0.5355,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.65851292,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7526538372039795},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7267047166824341},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.71646648645401},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6848330497741699},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.573845624923706},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5548807978630066},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.5447995066642761},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5250556468963623},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.524695098400116},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5186564326286316},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.508300244808197},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4636688232421875},{"id":"https://openalex.org/keywords/network-analysis","display_name":"Network analysis","score":0.4490188956260681},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.4296518564224243},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.41065680980682373},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35807639360427856},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2972583472728729},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24063479900360107},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15827763080596924},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11834326386451721}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7526538372039795},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7267047166824341},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.71646648645401},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6848330497741699},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.573845624923706},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5548807978630066},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.5447995066642761},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5250556468963623},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.524695098400116},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5186564326286316},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.508300244808197},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4636688232421875},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.4490188956260681},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.4296518564224243},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.41065680980682373},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35807639360427856},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2972583472728729},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24063479900360107},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15827763080596924},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11834326386451721},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dft59622.2023.10313533","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft59622.2023.10313533","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5899999737739563}],"awards":[],"funders":[{"id":"https://openalex.org/F4320326537","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31"},{"id":"https://openalex.org/F4320327859","display_name":"Hellenic Foundation for Research and Innovation","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1503456489","https://openalex.org/W1984588379","https://openalex.org/W2001575960","https://openalex.org/W2038126028","https://openalex.org/W2054113966","https://openalex.org/W2070284551","https://openalex.org/W2078825551","https://openalex.org/W2144038574","https://openalex.org/W2149041233","https://openalex.org/W2151691428","https://openalex.org/W2158102622","https://openalex.org/W2162318113","https://openalex.org/W2180580882","https://openalex.org/W2618494826","https://openalex.org/W2889003437","https://openalex.org/W2904722545","https://openalex.org/W4247874551","https://openalex.org/W4308654939","https://openalex.org/W6945921273"],"related_works":["https://openalex.org/W2059530328","https://openalex.org/W3011978806","https://openalex.org/W2743305891","https://openalex.org/W3205162826","https://openalex.org/W3168383044","https://openalex.org/W3207169898","https://openalex.org/W3198354237","https://openalex.org/W2951650892","https://openalex.org/W2331259470","https://openalex.org/W1596716095"],"abstract_inverted_index":{"The":[0],"manufacturing":[1],"of":[2,23,31,68,91,98],"modern":[3],"Integrated":[4],"Circuits":[5],"(IC),":[6],"resistant":[7],"to":[8,19,36,102],"faults":[9],"caused":[10],"by":[11],"ionising":[12],"radiation,":[13],"has":[14],"become":[15],"quite":[16],"challenging":[17],"due":[18],"the":[20,74,89,99],"rapid":[21],"advancement":[22],"VLSI":[24,64],"technology.":[25],"Existing":[26],"literature":[27],"employs":[28],"a":[29,49,84,111,117],"combination":[30],"simulation-based":[32],"and":[33],"analytical":[34],"methods":[35],"achieve":[37],"efficient":[38],"Single":[39],"Event":[40],"Transients":[41],"(SET)":[42],"analysis.":[43],"In":[44],"this":[45],"work,":[46],"we":[47],"propose":[48],"novel":[50],"Electronic":[51],"Design":[52],"Automation":[53],"(EDA)":[54],"analysis":[55,105],"approach":[56],"for":[57],"SETs,":[58],"called":[59],"UPSET.":[60],"UPSET":[61],"can":[62],"handle":[63],"circuits":[65],"with":[66,121],"thousands":[67],"gates":[69],"since":[70],"it":[71,82],"relies":[72],"on":[73],"industry-proven":[75],"Static":[76],"Timing":[77],"Analysis":[78],"(STA)":[79],"methodology.":[80],"Notably,":[81],"performs":[83],"complete":[85],"SET":[86],"analysis,":[87],"without":[88],"need":[90],"extra":[92],"characterisation,":[93],"while":[94,115],"providing":[95,116],"an":[96],"understanding":[97],"circuit":[100],"sensitivity":[101],"SETs.":[103],"Experimental":[104],"demonstrates":[106],"that":[107],"our":[108],"methodology":[109],"achieves":[110],"significant":[112],"\u00d725,222":[113],"speedup,":[114],"tight":[118],"upper":[119],"bound":[120],"4.56%":[122],"relative":[123],"error,":[124],"against":[125],"SPICE":[126],"simulation.":[127]},"counts_by_year":[{"year":2025,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
