{"id":"https://openalex.org/W3211307866","doi":"https://doi.org/10.1109/dft52944.2021.9568368","title":"A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design","display_name":"A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design","publication_year":2021,"publication_date":"2021-10-06","ids":{"openalex":"https://openalex.org/W3211307866","doi":"https://doi.org/10.1109/dft52944.2021.9568368","mag":"3211307866"},"language":"en","primary_location":{"id":"doi:10.1109/dft52944.2021.9568368","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft52944.2021.9568368","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002051086","display_name":"Marcello Barbirotta","orcid":"https://orcid.org/0000-0002-1902-7188"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marcello Barbirotta","raw_affiliation_strings":["\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","\"La Sapienza\" University of Rome, Via Eudossiana, Rome"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"\"La Sapienza\" University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060706503","display_name":"Abdallah Cheikh","orcid":"https://orcid.org/0000-0003-4495-5960"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Abdallah Cheikh","raw_affiliation_strings":["\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","\"La Sapienza\" University of Rome, Via Eudossiana, Rome"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"\"La Sapienza\" University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044942957","display_name":"Antonio Mastrandrea","orcid":"https://orcid.org/0000-0003-4243-1258"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Antonio Mastrandrea","raw_affiliation_strings":["\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","\"La Sapienza\" University of Rome, Via Eudossiana, Rome"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"\"La Sapienza\" University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045257843","display_name":"Francesco Menichelli","orcid":null},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco Menichelli","raw_affiliation_strings":["\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","\"La Sapienza\" University of Rome, Via Eudossiana, Rome"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"\"La Sapienza\" University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071897263","display_name":"Francesco Vigli","orcid":"https://orcid.org/0009-0003-3882-5147"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco Vigli","raw_affiliation_strings":["\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","\"La Sapienza\" University of Rome, Via Eudossiana, Rome"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"\"La Sapienza\" University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067054447","display_name":"Mauro Olivieri","orcid":"https://orcid.org/0000-0002-0214-9904"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mauro Olivieri","raw_affiliation_strings":["\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","\"La Sapienza\" University of Rome, Via Eudossiana, Rome"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"\u201cLa Sapienza\u201d University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"\"La Sapienza\" University of Rome, Via Eudossiana, Rome","institution_ids":["https://openalex.org/I861853513"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I861853513"],"apc_list":null,"apc_paid":null,"fwci":1.2785,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.79839767,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7960643768310547},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.7092042565345764},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6471970081329346},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6279062032699585},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6118223667144775},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5985209941864014},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.5965940356254578},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5591722726821899},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.5533270835876465},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47677305340766907},{"id":"https://openalex.org/keywords/threading","display_name":"Threading (protein sequence)","score":0.4756314754486084},{"id":"https://openalex.org/keywords/fault-injection","display_name":"Fault injection","score":0.4644145369529724},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.43770238757133484},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4373116195201874},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.3099524676799774},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18107691407203674}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7960643768310547},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.7092042565345764},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6471970081329346},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6279062032699585},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6118223667144775},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5985209941864014},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.5965940356254578},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5591722726821899},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.5533270835876465},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47677305340766907},{"id":"https://openalex.org/C200307862","wikidata":"https://www.wikidata.org/wiki/Q7797175","display_name":"Threading (protein sequence)","level":3,"score":0.4756314754486084},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.4644145369529724},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.43770238757133484},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4373116195201874},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3099524676799774},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18107691407203674},{"id":"https://openalex.org/C47701112","wikidata":"https://www.wikidata.org/wiki/Q735188","display_name":"Protein structure","level":2,"score":0.0},{"id":"https://openalex.org/C46141821","wikidata":"https://www.wikidata.org/wiki/Q209402","display_name":"Nuclear magnetic resonance","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dft52944.2021.9568368","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft52944.2021.9568368","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.uniroma1.it:11573/1622494","is_oa":false,"landing_page_url":"https://hdl.handle.net/11573/1622494","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W2118959189","https://openalex.org/W2148644350","https://openalex.org/W2216222290","https://openalex.org/W2757706453","https://openalex.org/W2790341792","https://openalex.org/W2904659759","https://openalex.org/W2929060078","https://openalex.org/W2943620027","https://openalex.org/W2976811221","https://openalex.org/W2995380782","https://openalex.org/W3042964438","https://openalex.org/W3100547819","https://openalex.org/W3104316274","https://openalex.org/W3118606186","https://openalex.org/W3201601181","https://openalex.org/W6744593015","https://openalex.org/W6785832982","https://openalex.org/W6786393643"],"related_works":["https://openalex.org/W2384903348","https://openalex.org/W4253890856","https://openalex.org/W2369027488","https://openalex.org/W3149034384","https://openalex.org/W2650626006","https://openalex.org/W2097410296","https://openalex.org/W76998001","https://openalex.org/W2378658106","https://openalex.org/W4234222745","https://openalex.org/W2133675875"],"abstract_inverted_index":{"Introducing":[0],"Fault":[1],"Tolerance":[2],"(FT)":[3],"in":[4,56],"designs":[5],"implemented":[6],"with":[7,143],"commercial-off-the-shelf":[8],"(COTS)":[9],"components,":[10],"such":[11],"as":[12,137],"FPGAs,":[13],"is":[14],"very":[15,51],"interesting":[16],"because":[17],"they":[18],"are":[19],"orders":[20],"of":[21,74,96,140],"magnitude":[22],"less":[23],"expensive":[24],"than":[25],"Rad-":[26],"Hard":[27],"components.":[28],"Significant":[29],"work":[30,116],"has":[31,53,66],"been":[32,54],"done":[33],"on":[34,38,59,78],"FT":[35,68,104,128],"architectures":[36],"based":[37],"functional":[39],"redundancy":[40],"through":[41,70],"multi-core":[42],"processors":[43],"or":[44],"Simultaneous":[45],"Multi":[46],"Thread":[47],"(SMT)":[48],"processors,":[49],"while":[50],"little":[52],"explored":[55],"this":[57,115],"direction":[58],"Interleaved":[60],"Multi-Threading":[61],"(IMT)":[62],"processors.":[63],"IMT":[64,83,107,119,133],"potentially":[65],"intrinsic":[67],"features":[69],"the":[71,75,90,131,138],"redundant":[72,91],"execution":[73,108],"same":[76],"task":[77],"multiple":[79],"interleaved":[80],"threads.":[81],"Also,":[82],"intrinsically":[84],"introduces":[85],"a":[86,106,126],"temporal":[87],"shift":[88],"among":[89],"instructions,":[92],"which":[93],"can":[94],"be":[95],"interest":[97],"for":[98],"specific":[99],"fault":[100],"situations.":[101],"Yet,":[102],"implementing":[103],"within":[105],"paradigm":[109],"requires":[110],"dedicated":[111],"hardware":[112,120],"management.":[113],"In":[114],"we":[117],"discuss":[118],"microarchitecture":[121],"modifications":[122],"needed":[123],"to":[124],"obtain":[125],"stable":[127],"processor,":[129],"using":[130],"RISCV":[132],"soft-core":[134],"Klessydra-":[135],"T13":[136],"basis":[139],"our":[141],"experiments":[142],"an":[144],"hard":[145],"Fault-Injection":[146],"simulation":[147],"campaign.":[148]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":3}],"updated_date":"2026-02-26T06:29:33.603293","created_date":"2025-10-10T00:00:00"}