{"id":"https://openalex.org/W3210094828","doi":"https://doi.org/10.1109/dft52944.2021.9568296","title":"Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits","display_name":"Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits","publication_year":2021,"publication_date":"2021-10-06","ids":{"openalex":"https://openalex.org/W3210094828","doi":"https://doi.org/10.1109/dft52944.2021.9568296","mag":"3210094828"},"language":"en","primary_location":{"id":"doi:10.1109/dft52944.2021.9568296","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft52944.2021.9568296","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057901469","display_name":"Stavros Simoglou","orcid":"https://orcid.org/0000-0003-0015-7510"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Stavros Simoglou","raw_affiliation_strings":["EECE Department, University of Thessaly, Volos, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"EECE Department, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103066371","display_name":"Christos Sotiriou","orcid":"https://orcid.org/0000-0001-9318-474X"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Christos Sotiriou","raw_affiliation_strings":["EECE Department, University of Thessaly, Volos, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"EECE Department, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063643730","display_name":"Nikolaos Blias","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Nikolaos Blias","raw_affiliation_strings":["EECE Department, University of Thessaly, Volos, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"EECE Department, University of Thessaly, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I145722265"],"apc_list":null,"apc_paid":null,"fwci":0.3934,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.60380612,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.8644601106643677},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8265959024429321},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.7472807168960571},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.71876460313797},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.48500868678092957},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.4799354672431946},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47930899262428284},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45618027448654175},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.43273842334747314},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4272415339946747},{"id":"https://openalex.org/keywords/slew-rate","display_name":"Slew rate","score":0.41788381338119507},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.41473495960235596},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4092535376548767},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.27226391434669495},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.19347426295280457},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.16819828748703003},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15228256583213806},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14082872867584229},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.12930774688720703},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.10200658440589905},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07481864094734192}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.8644601106643677},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8265959024429321},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.7472807168960571},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.71876460313797},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.48500868678092957},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4799354672431946},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47930899262428284},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45618027448654175},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.43273842334747314},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4272415339946747},{"id":"https://openalex.org/C82517063","wikidata":"https://www.wikidata.org/wiki/Q1591315","display_name":"Slew rate","level":3,"score":0.41788381338119507},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.41473495960235596},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4092535376548767},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.27226391434669495},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.19347426295280457},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.16819828748703003},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15228256583213806},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14082872867584229},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.12930774688720703},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.10200658440589905},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07481864094734192},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dft52944.2021.9568296","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft52944.2021.9568296","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},{"id":"pmh:oai:ir.lib.uth.gr:11615/78986","is_oa":false,"landing_page_url":"http://hdl.handle.net/11615/78986","pdf_url":null,"source":{"id":"https://openalex.org/S4306400243","display_name":"University of Thessaly Institutional Repository (University of Thessaly)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I145722265","host_organization_name":"University of Thessaly","host_organization_lineage":["https://openalex.org/I145722265"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT","raw_type":"conferenceItem"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1984588379","https://openalex.org/W2160823654","https://openalex.org/W2607359301","https://openalex.org/W2914903263","https://openalex.org/W2979377739","https://openalex.org/W3035068031","https://openalex.org/W3047136511"],"related_works":["https://openalex.org/W2131965086","https://openalex.org/W2127888129","https://openalex.org/W2122690047","https://openalex.org/W2237508561","https://openalex.org/W3210094828","https://openalex.org/W2072530605","https://openalex.org/W3199501896","https://openalex.org/W1500562608","https://openalex.org/W2102154383","https://openalex.org/W1952379751"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"demonstrate":[4,108],"that":[5,131],"conventional":[6],"Static":[7],"Timing":[8],"Anaysis":[9],"(STA)":[10],"based,":[11],"functional,":[12],"gate-level":[13,100],"simulation":[14,133,147],"of":[15,61,111],"asynchronous":[16,116],"circuits":[17],"with":[18,102],"cycles":[19,77],"is":[20,78,143,156],"only":[21],"as":[22,24,86],"accurate":[23],"the":[25,56,109,121,146],"STA":[26,64,97],"engine":[27],"used.":[28],"This":[29],"is,":[30],"firstly":[31],"because":[32,43],"cycle":[33],"cuts":[34],"create":[35],"local":[36],"slew":[37,44],"errors":[38,113],"at":[39],"cutpoints,":[40],"and":[41,72,98,141],"secondly":[42],"propagation":[45],"may":[46],"not":[47,69],"be":[48,151],"upper":[49,88],"bounded":[50],"across":[51,76],"multiple":[52],"cut":[53,70],"points":[54],"in":[55,124],"same":[57],"cycle.":[58],"The":[59],"use":[60],"an":[62,87],"Asynchronous":[63],"(ASTA)":[65],"engine,":[66],"which":[67,82,155],"does":[68],"cycles,":[71],"properly":[73],"bounds":[74],"slews":[75],"a":[79,125,157],"possible":[80,144],"solution,":[81],"can":[83],"indeed":[84],"serve":[85],"bound":[89],"over":[90],"SPICE":[91,105],"transistor":[92,103],"level":[93,104],"similations.":[94],"We":[95,129],"contrast":[96],"ASTA-based":[99],"simulations":[101,106],"to":[107,149],"impact":[110],"timing":[112,159],"for":[114,145],"12":[115],"control":[117],"circuits,":[118],"implemented":[119],"by":[120],"Petrify":[122],"tool,":[123],"0.25\u03bcm":[126],"technology":[127],"library.":[128],"show":[130],"STA-based":[132],"results":[134],"are":[135],"incorrectly":[136],"more":[137],"optimistic":[138],"than":[139,153],"ASTA,":[140],"it":[142],"period":[148],"even":[150],"faster":[152],"SPICE,":[154],"major":[158],"error.":[160]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2}],"updated_date":"2026-07-10T05:49:55.623906","created_date":"2025-10-10T00:00:00"}
