{"id":"https://openalex.org/W2982095185","doi":"https://doi.org/10.1109/dft.2019.8875457","title":"CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore","display_name":"CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W2982095185","doi":"https://doi.org/10.1109/dft.2019.8875457","mag":"2982095185"},"language":"en","primary_location":{"id":"doi:10.1109/dft.2019.8875457","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2019.8875457","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051728516","display_name":"Avishek Choudhury","orcid":"https://orcid.org/0000-0001-6046-7559"},"institutions":[{"id":"https://openalex.org/I180765649","display_name":"Aliah University","ror":"https://ror.org/03rfycd69","country_code":"IN","type":"education","lineage":["https://openalex.org/I180765649"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Avishek Choudhury","raw_affiliation_strings":["Department of Computer Science, New Alipore College, Kolkata, India","New Alipore College, New Alipore, Kolkata, 700053, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, New Alipore College, Kolkata, India","institution_ids":["https://openalex.org/I180765649"]},{"raw_affiliation_string":"New Alipore College, New Alipore, Kolkata, 700053, India","institution_ids":["https://openalex.org/I180765649"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089134920","display_name":"Biplab K. Sikdar","orcid":"https://orcid.org/0000-0002-9394-8540"},"institutions":[{"id":"https://openalex.org/I98365261","display_name":"Indian Institute of Engineering Science and Technology, Shibpur","ror":"https://ror.org/02ytfzr55","country_code":"IN","type":"education","lineage":["https://openalex.org/I98365261"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Biplab K Sikdar","raw_affiliation_strings":["Department of Computer Science & Technology, Indian Institute of Enginering, Science & Technology, Howrah","Indian Institute of Enginering, Science & Technology, Shibpur, Howrah, 711103"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science & Technology, Indian Institute of Enginering, Science & Technology, Howrah","institution_ids":[]},{"raw_affiliation_string":"Indian Institute of Enginering, Science & Technology, Shibpur, Howrah, 711103","institution_ids":["https://openalex.org/I98365261"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13699671,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"10","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reusability","display_name":"Reusability","score":0.7822525501251221},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.7769440412521362},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7111091613769531},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5573832392692566},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.5121333599090576},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.4786897301673889},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.4764045774936676},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45601633191108704},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.4457663297653198},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4400936961174011},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.2819404900074005},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.2460845708847046},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21691814064979553},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.06465652585029602},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.061131566762924194}],"concepts":[{"id":"https://openalex.org/C137981799","wikidata":"https://www.wikidata.org/wiki/Q1369184","display_name":"Reusability","level":3,"score":0.7822525501251221},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.7769440412521362},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7111091613769531},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5573832392692566},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.5121333599090576},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.4786897301673889},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.4764045774936676},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45601633191108704},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.4457663297653198},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4400936961174011},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.2819404900074005},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.2460845708847046},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21691814064979553},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.06465652585029602},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.061131566762924194}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dft.2019.8875457","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2019.8875457","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5600000023841858,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2002038549","https://openalex.org/W2031948068","https://openalex.org/W2033381896","https://openalex.org/W2056592359","https://openalex.org/W2109432325","https://openalex.org/W2134682810","https://openalex.org/W2143134476","https://openalex.org/W2157447136","https://openalex.org/W2159774216","https://openalex.org/W2167188929","https://openalex.org/W2170382128","https://openalex.org/W2464177207","https://openalex.org/W2537959404","https://openalex.org/W4231535434","https://openalex.org/W4238002809"],"related_works":["https://openalex.org/W4285204597","https://openalex.org/W2290195868","https://openalex.org/W3193874149","https://openalex.org/W2139534474","https://openalex.org/W2584505417","https://openalex.org/W2013212244","https://openalex.org/W2002047509","https://openalex.org/W2352722396","https://openalex.org/W2107914397","https://openalex.org/W3026856133"],"abstract_inverted_index":{"Voltage":[0],"scaling":[1],"to":[2,16,59,86,104],"reduce":[3],"power":[4,61,129,133],"consumption":[5],"for":[6,108],"ensuring":[7],"longer":[8],"battery":[9],"life":[10],"expedites":[11],"SRAM":[12],"cell":[13,26],"failures":[14,27],"due":[15],"process":[17],"variations.":[18],"Cache,":[19],"holding":[20],"significant":[21],"chip":[22],"area,":[23],"encounters":[24],"these":[25],"exponentially":[28],"with":[29,122,126],"voltage":[30,33],"reduction.":[31],"Several":[32],"reduction":[34],"techniques":[35],"have":[36],"been":[37],"proposed":[38],"by":[39,64],"tolerating":[40],"faults":[41,66],"at":[42],"the":[43],"cost":[44],"of":[45],"sacrificial":[46],"cache":[47,51,70,79,88,113],"portions":[48,80],"affecting":[49,68],"effective":[50,69,112],"capacity.":[52,71,114],"On":[53],"this":[54,56],"outset,":[55],"work":[57,116],"attempts":[58],"minimize":[60],"below":[62],"threshold":[63],"handling":[65],"without":[67],"Words":[72],"under":[73],"priority":[74],"blocks":[75,85],"addressed":[76],"on":[77],"faulty":[78],"are":[81,91,102],"remapped":[82],"in":[83,135],"non-functional":[84],"avoid":[87],"pollution.":[89],"Blocks":[90],"prioritized":[92],"considering":[93],"their":[94],"coherence":[95],"states":[96],"and":[97,110,130],"reusability.":[98],"Non-reusable":[99],"clean":[100],"copies":[101],"invalidated":[103],"ensure":[105],"adequate":[106],"space":[107],"remapping":[109],"maintaining":[111],"This":[115],"achieves":[117],"minimum":[118],"Vdd":[119],"325":[120],"mV":[121],"7.77%":[123],"area":[124],"overhead":[125,134],"6.7%":[127],"leakage":[128],"0.5%":[131],"dynamic":[132],"90nm":[136],"processor.":[137]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
