{"id":"https://openalex.org/W2909409513","doi":"https://doi.org/10.1109/dft.2018.8602988","title":"Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders","display_name":"Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2909409513","doi":"https://doi.org/10.1109/dft.2018.8602988","mag":"2909409513"},"language":"en","primary_location":{"id":"doi:10.1109/dft.2018.8602988","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2018.8602988","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054396881","display_name":"Zhen Gao","orcid":"https://orcid.org/0000-0002-2709-0216"},"institutions":[{"id":"https://openalex.org/I162868743","display_name":"Tianjin University","ror":"https://ror.org/012tb2g32","country_code":"CN","type":"education","lineage":["https://openalex.org/I162868743"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhen Gao","raw_affiliation_strings":["School of Electrical and Information Engineering, Tianjin University, Tianjin, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Information Engineering, Tianjin University, Tianjin, China","institution_ids":["https://openalex.org/I162868743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019789757","display_name":"Lina Yan","orcid":null},"institutions":[{"id":"https://openalex.org/I162868743","display_name":"Tianjin University","ror":"https://ror.org/012tb2g32","country_code":"CN","type":"education","lineage":["https://openalex.org/I162868743"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lina Yan","raw_affiliation_strings":["School of Electrical and Information Engineering, Tianjin University, Tianjin, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Information Engineering, Tianjin University, Tianjin, China","institution_ids":["https://openalex.org/I162868743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028284977","display_name":"Jinhua Zhu","orcid":"https://orcid.org/0000-0003-2157-9077"},"institutions":[{"id":"https://openalex.org/I162868743","display_name":"Tianjin University","ror":"https://ror.org/012tb2g32","country_code":"CN","type":"education","lineage":["https://openalex.org/I162868743"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinhua Zhu","raw_affiliation_strings":["School of Electrical and Information Engineering, Tianjin University, Tianjin, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Information Engineering, Tianjin University, Tianjin, China","institution_ids":["https://openalex.org/I162868743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032975404","display_name":"Ruishi Han","orcid":null},"institutions":[{"id":"https://openalex.org/I162868743","display_name":"Tianjin University","ror":"https://ror.org/012tb2g32","country_code":"CN","type":"education","lineage":["https://openalex.org/I162868743"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ruishi Han","raw_affiliation_strings":["School of Electrical and Information Engineering, Tianjin University, Tianjin, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Information Engineering, Tianjin University, Tianjin, China","institution_ids":["https://openalex.org/I162868743"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080322790","display_name":"Pedro Reviriego","orcid":"https://orcid.org/0000-0003-2540-5234"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Reviriego","raw_affiliation_strings":["ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/viterbi-decoder","display_name":"Viterbi decoder","score":0.855053722858429},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8267993927001953},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6996527910232544},{"id":"https://openalex.org/keywords/soft-decision-decoder","display_name":"Soft-decision decoder","score":0.6882221102714539},{"id":"https://openalex.org/keywords/viterbi-algorithm","display_name":"Viterbi algorithm","score":0.6179018020629883},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.5987906455993652},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.5965446829795837},{"id":"https://openalex.org/keywords/soft-output-viterbi-algorithm","display_name":"Soft output Viterbi algorithm","score":0.5177351832389832},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.4985635280609131},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.46943214535713196},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.45259925723075867},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4447661340236664},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4285701513290405},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1953607201576233},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.16279083490371704},{"id":"https://openalex.org/keywords/sequential-decoding","display_name":"Sequential decoding","score":0.14846819639205933},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07585868239402771},{"id":"https://openalex.org/keywords/block-code","display_name":"Block code","score":0.06740310788154602}],"concepts":[{"id":"https://openalex.org/C117379686","wikidata":"https://www.wikidata.org/wiki/Q6996459","display_name":"Viterbi decoder","level":3,"score":0.855053722858429},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8267993927001953},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6996527910232544},{"id":"https://openalex.org/C185588885","wikidata":"https://www.wikidata.org/wiki/Q7553811","display_name":"Soft-decision decoder","level":3,"score":0.6882221102714539},{"id":"https://openalex.org/C60582962","wikidata":"https://www.wikidata.org/wiki/Q83886","display_name":"Viterbi algorithm","level":3,"score":0.6179018020629883},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.5987906455993652},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.5965446829795837},{"id":"https://openalex.org/C130319729","wikidata":"https://www.wikidata.org/wiki/Q83886","display_name":"Soft output Viterbi algorithm","level":5,"score":0.5177351832389832},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.4985635280609131},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.46943214535713196},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.45259925723075867},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4447661340236664},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4285701513290405},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1953607201576233},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.16279083490371704},{"id":"https://openalex.org/C193969084","wikidata":"https://www.wikidata.org/wiki/Q7452500","display_name":"Sequential decoding","level":4,"score":0.14846819639205933},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07585868239402771},{"id":"https://openalex.org/C157125643","wikidata":"https://www.wikidata.org/wiki/Q884707","display_name":"Block code","level":3,"score":0.06740310788154602},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dft.2018.8602988","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2018.8602988","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W571536966","https://openalex.org/W1512085033","https://openalex.org/W1580543952","https://openalex.org/W1607327922","https://openalex.org/W1984314538","https://openalex.org/W1991133427","https://openalex.org/W2008526643","https://openalex.org/W2159329043","https://openalex.org/W2168323440","https://openalex.org/W2475646144","https://openalex.org/W2541133130","https://openalex.org/W2546241309","https://openalex.org/W6630600501","https://openalex.org/W6634799193"],"related_works":["https://openalex.org/W2161773370","https://openalex.org/W2133857928","https://openalex.org/W2367491988","https://openalex.org/W2356694334","https://openalex.org/W120707411","https://openalex.org/W2783469447","https://openalex.org/W2790444905","https://openalex.org/W2146383045","https://openalex.org/W2140390573","https://openalex.org/W2382058016"],"abstract_inverted_index":{"This":[0],"paper":[1],"analyzes":[2],"the":[3,11,34,43,63,66,83,87,92,94,98,108,113,130,141,144],"effects":[4],"of":[5,14,49,74,97,112,117,140],"single":[6],"event":[7],"upsets":[8],"(SEUs)":[9],"on":[10,19,76,119],"user":[12,40,77,120],"memory":[13],"a":[15,137],"Viterbi":[16,27,84],"decoder":[17,28,142],"implemented":[18],"an":[20,25],"SRAM":[21],"based":[22],"FPGA.":[23],"First,":[24],"FPGA":[26],"implementation":[29],"is":[30,52],"used":[31,134],"to":[32,39,61,135],"study":[33],"structures":[35,51],"that":[36,72,106],"are":[37,59],"mapped":[38],"memory.":[41],"Then,":[42],"SEUs":[44,75,118,126],"tolerance":[45,96,127],"capability":[46],"for":[47,101],"each":[48],"those":[50],"analyzed":[53],"theoretically.":[54],"Finally,":[55],"fault":[56,95],"injection":[57],"experiments":[58],"performed":[60],"verify":[62],"analysis.":[64],"Both":[65],"analysis":[67,128],"and":[68,86,129],"experiment":[69],"results":[70,131],"show":[71],"most":[73],"memories":[78,121],"can":[79,122],"be":[80,123,133],"tolerated":[81],"by":[82],"decoder,":[85,114],"lower":[88],"bit":[89,103],"error":[90,104,109],"rate,":[91],"better":[93],"decoder.":[99],"Even":[100],"high":[102],"rate":[105],"exceeds":[107],"correction":[110],"limit":[111],"over":[115],"95%":[116],"tolerated.":[124],"The":[125],"will":[132],"implement":[136],"selective":[138],"hardening":[139],"in":[143],"future.":[145]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}