{"id":"https://openalex.org/W2908829047","doi":"https://doi.org/10.1109/dft.2018.8602982","title":"Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors","display_name":"Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2908829047","doi":"https://doi.org/10.1109/dft.2018.8602982","mag":"2908829047"},"language":"en","primary_location":{"id":"doi:10.1109/dft.2018.8602982","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2018.8602982","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040853255","display_name":"A. Floridia","orcid":"https://orcid.org/0000-0003-2766-9188"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"A. Floridia","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009336869","display_name":"Ernesto S\u00e1nchez","orcid":"https://orcid.org/0000-0002-7042-295X"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"E. Sanchez","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5040853255"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":0.9013,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.77011752,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7515386343002319},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.6474765539169312},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5878585577011108},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5751248002052307},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5383402705192566},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.49277618527412415},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4855906367301941},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.4703141748905182},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4564093053340912},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3862055838108063},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33233538269996643},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22562816739082336},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13751479983329773}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7515386343002319},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.6474765539169312},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5878585577011108},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5751248002052307},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5383402705192566},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.49277618527412415},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4855906367301941},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.4703141748905182},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4564093053340912},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3862055838108063},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33233538269996643},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22562816739082336},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13751479983329773},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dft.2018.8602982","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2018.8602982","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.4399999976158142,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1968989269","https://openalex.org/W2033613342","https://openalex.org/W2043369860","https://openalex.org/W2045015510","https://openalex.org/W2106864957","https://openalex.org/W2132836329","https://openalex.org/W2162736794","https://openalex.org/W2609234282","https://openalex.org/W2752260471","https://openalex.org/W2767807890","https://openalex.org/W4233573690"],"related_works":["https://openalex.org/W2034349229","https://openalex.org/W4366783034","https://openalex.org/W1972415042","https://openalex.org/W4313221225","https://openalex.org/W2150642609","https://openalex.org/W2005410346","https://openalex.org/W4306816370","https://openalex.org/W2189390720","https://openalex.org/W2390229089","https://openalex.org/W2951548045"],"abstract_inverted_index":{"Multi-core":[0],"processors":[1],"are":[2,27],"increasingly":[3],"becoming":[4],"popular":[5],"even":[6],"in":[7,35,86],"safety-critical":[8],"applications,":[9],"and":[10],"the":[11,54,58,80,105],"compliance":[12],"of":[13,32,57,68,95,104],"such":[14],"systems":[15],"with":[16,29,88],"functional":[17],"safety":[18],"standards":[19],"is":[20,41,61],"thus":[21],"mandatory.":[22],"The":[23,71,93],"targeted":[24],"reliability":[25],"figures":[26],"achieved":[28],"a":[30,37,50,89,101],"combination":[31],"different":[33],"solutions,":[34],"particular":[36],"largely":[38],"employed":[39],"one":[40],"named":[42],"Dual-Core":[43],"Lockstep":[44],"(DCLS)":[45],"configuration.":[46],"In":[47],"this":[48,96],"paper,":[49],"hybrid":[51],"scheme":[52],"for":[53,64],"on-line":[55],"testing":[56],"lockstep":[59,69],"logic":[60],"proposed,":[62],"allowing":[63],"non-intrusive":[65],"run-time":[66],"test":[67,75],"comparators.":[70],"proposed":[72],"solution":[73],"leverages":[74],"programs":[76],"developed":[77],"according":[78],"to":[79],"Software-Based":[81],"Self-Test":[82],"(SBST)":[83],"approach,":[84],"used":[85],"conjunction":[87],"specialized":[90],"hardware":[91],"module.":[92],"effectiveness":[94],"approach":[97],"was":[98],"assessed":[99],"on":[100],"modified":[102],"version":[103],"OpenRISC":[106],"1200":[107],"processor,":[108],"considering":[109],"stuck-at":[110],"faults":[111],"only.":[112]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}