{"id":"https://openalex.org/W2544652054","doi":"https://doi.org/10.1109/dft.2016.7684074","title":"In-place LUT polarity inVersion to mitigate soft errors for FPGAs","display_name":"In-place LUT polarity inVersion to mitigate soft errors for FPGAs","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2544652054","doi":"https://doi.org/10.1109/dft.2016.7684074","mag":"2544652054"},"language":"en","primary_location":{"id":"doi:10.1109/dft.2016.7684074","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2016.7684074","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039242808","display_name":"Juexiao Su","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Juexiao Su","raw_affiliation_strings":["EE Dept., Univeristy of California, Los Angeles, United States"],"affiliations":[{"raw_affiliation_string":"EE Dept., Univeristy of California, Los Angeles, United States","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080021968","display_name":"Ju-Yueh Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ju-Yueh Lee","raw_affiliation_strings":["EE Dept., Univeristy of California, Los Angeles, United States"],"affiliations":[{"raw_affiliation_string":"EE Dept., Univeristy of California, Los Angeles, United States","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101530541","display_name":"Chang Wu","orcid":"https://orcid.org/0000-0003-2590-6338"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chang Wu","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008695429","display_name":"Lei He","orcid":"https://orcid.org/0000-0002-5266-3805"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lei He","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5039242808"],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":0.3675,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.66616377,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"18","issue":null,"first_page":"81","last_page":"86"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8443354368209839},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7842278480529785},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6970888376235962},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.6345382332801819},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.6234856843948364},{"id":"https://openalex.org/keywords/inversion","display_name":"Inversion (geology)","score":0.47027164697647095},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4600510597229004},{"id":"https://openalex.org/keywords/single-event-upset","display_name":"Single event upset","score":0.42658495903015137},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41864538192749023},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.392845094203949},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3271116018295288},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.19871345162391663},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14249280095100403},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10863760113716125},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.07525360584259033}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8443354368209839},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7842278480529785},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6970888376235962},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.6345382332801819},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.6234856843948364},{"id":"https://openalex.org/C1893757","wikidata":"https://www.wikidata.org/wiki/Q3653001","display_name":"Inversion (geology)","level":3,"score":0.47027164697647095},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4600510597229004},{"id":"https://openalex.org/C2780073065","wikidata":"https://www.wikidata.org/wiki/Q1476733","display_name":"Single event upset","level":3,"score":0.42658495903015137},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41864538192749023},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.392845094203949},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3271116018295288},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.19871345162391663},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14249280095100403},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10863760113716125},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.07525360584259033},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C109007969","wikidata":"https://www.wikidata.org/wiki/Q749565","display_name":"Structural basin","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dft.2016.7684074","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2016.7684074","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W160422864","https://openalex.org/W1964218206","https://openalex.org/W1970885193","https://openalex.org/W2015213746","https://openalex.org/W2039188166","https://openalex.org/W2045206490","https://openalex.org/W2046363763","https://openalex.org/W2046549786","https://openalex.org/W2104402818","https://openalex.org/W2166579337","https://openalex.org/W2171549192","https://openalex.org/W3142488006","https://openalex.org/W3146295682","https://openalex.org/W3152239234","https://openalex.org/W4240833370","https://openalex.org/W4254542277"],"related_works":["https://openalex.org/W2622269177","https://openalex.org/W1523508240","https://openalex.org/W2102538861","https://openalex.org/W1576787868","https://openalex.org/W2122334461","https://openalex.org/W2096742257","https://openalex.org/W2165400042","https://openalex.org/W4211237868","https://openalex.org/W2086616086","https://openalex.org/W4221121827"],"abstract_inverted_index":{"In-place":[0],"Polarity":[1],"inVersion":[2],"(IPV)":[3],"has":[4],"been":[5],"proposed":[6],"to":[7,80,89,111,115],"mitigate":[8],"the":[9,26,41,66,90,116],"single":[10],"event":[11],"upset":[12],"(SEU)":[13],"induced":[14],"soft":[15,48,102],"errors":[16,103],"for":[17,35],"academic":[18],"VPR":[19],"FPGA":[20,37],"architectures,":[21],"and":[22,55,86,109],"this":[23],"paper":[24],"extends":[25],"original":[27,42],"IPV":[28,69,78,99,122],"so":[29],"that":[30,98],"it":[31],"can":[32],"be":[33],"used":[34],"commercial":[36],"architectures.":[38],"Different":[39],"from":[40],"IPV,":[43],"we":[44,71],"use":[45],"a":[46,57,81],"new":[47],"error":[49],"model":[50],"based":[51,62],"on":[52,107],"signal":[53],"probability":[54],"propose":[56],"simple":[58],"yet":[59],"effective":[60],"greedy":[61],"algorithm.":[63],"To":[64],"validate":[65],"effectiveness":[67],"of":[68],"2.0,":[70],"map":[72],"circuits":[73,92,117],"by":[74,77,104,119],"ISE":[75,120],"followed":[76],"2.0":[79,100],"Xilinx":[82],"Virtex-5":[83],"x5vlx110t":[84],"FPGA,":[85],"inject":[87],"faults":[88],"mapped":[91,118],"during":[93],"run":[94],"time.":[95],"Experiments":[96],"show":[97],"reduces":[101],"about":[105],"1.4\u00d7":[106],"average":[108],"up":[110],"2\u00d7":[112],"when":[113],"compared":[114],"without":[121],"2.0.":[123]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
