{"id":"https://openalex.org/W1976676587","doi":"https://doi.org/10.1109/dft.2013.6653622","title":"BIST for logic and local interconnect resources in a novel mesh of cluster FPGA","display_name":"BIST for logic and local interconnect resources in a novel mesh of cluster FPGA","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W1976676587","doi":"https://doi.org/10.1109/dft.2013.6653622","mag":"1976676587"},"language":"en","primary_location":{"id":"doi:10.1109/dft.2013.6653622","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2013.6653622","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083788386","display_name":"Saif-Ur Rehman","orcid":null},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I177483745","display_name":"Universit\u00e9 Joseph Fourier","ror":"https://ror.org/02aj0kh94","country_code":"FR","type":"education","lineage":["https://openalex.org/I177483745"]},{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Saif-Ur Rehman","raw_affiliation_strings":["TIM A Laboratory (INP-Grenoble DJF, CNRS), France","TIMA Lab., UJF, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIM A Laboratory (INP-Grenoble DJF, CNRS), France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., UJF, Grenoble, France","institution_ids":["https://openalex.org/I177483745","https://openalex.org/I4210087012","https://openalex.org/I899635006"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108093269","display_name":"Mounir Benabdenbi","orcid":"https://orcid.org/0000-0001-9586-3009"},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I177483745","display_name":"Universit\u00e9 Joseph Fourier","ror":"https://ror.org/02aj0kh94","country_code":"FR","type":"education","lineage":["https://openalex.org/I177483745"]},{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Mounir Benabdenbi","raw_affiliation_strings":["TIM A Laboratory (INP-Grenoble DJF, CNRS), France","TIMA Lab., UJF, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIM A Laboratory (INP-Grenoble DJF, CNRS), France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., UJF, Grenoble, France","institution_ids":["https://openalex.org/I177483745","https://openalex.org/I4210087012","https://openalex.org/I899635006"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053835664","display_name":"Lorena Anghel","orcid":"https://orcid.org/0000-0001-9569-0072"},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I177483745","display_name":"Universit\u00e9 Joseph Fourier","ror":"https://ror.org/02aj0kh94","country_code":"FR","type":"education","lineage":["https://openalex.org/I177483745"]},{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Lorena Anghel","raw_affiliation_strings":["TIM A Laboratory (INP-Grenoble DJF, CNRS), France","TIMA Lab., UJF, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIM A Laboratory (INP-Grenoble DJF, CNRS), France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., UJF, Grenoble, France","institution_ids":["https://openalex.org/I177483745","https://openalex.org/I4210087012","https://openalex.org/I899635006"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8966,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.70116559,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"296","last_page":"301"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8456075191497803},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7441542744636536},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6719767451286316},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6503015756607056},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6197241544723511},{"id":"https://openalex.org/keywords/cluster","display_name":"Cluster (spacecraft)","score":0.5683140158653259},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48038250207901},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45438799262046814},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.44411033391952515},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34184059500694275},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33657461404800415},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19077789783477783},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.15419170260429382},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0648973286151886}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8456075191497803},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7441542744636536},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6719767451286316},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6503015756607056},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6197241544723511},{"id":"https://openalex.org/C164866538","wikidata":"https://www.wikidata.org/wiki/Q367351","display_name":"Cluster (spacecraft)","level":2,"score":0.5683140158653259},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48038250207901},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45438799262046814},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.44411033391952515},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34184059500694275},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33657461404800415},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19077789783477783},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.15419170260429382},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0648973286151886},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dft.2013.6653622","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2013.6653622","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00982772v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00982772","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2013, New-York, United States. pp.296 - 301, &#x27E8;10.1109/DFT.2013.6653622&#x27E9;","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5400000214576721,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W53227076","https://openalex.org/W54040206","https://openalex.org/W1523051745","https://openalex.org/W1524155523","https://openalex.org/W1530208162","https://openalex.org/W1603523129","https://openalex.org/W2011456762","https://openalex.org/W2013253017","https://openalex.org/W2047199967","https://openalex.org/W2119841103","https://openalex.org/W2123552323","https://openalex.org/W2124403117","https://openalex.org/W2141228178","https://openalex.org/W2145643756","https://openalex.org/W2152577665","https://openalex.org/W2155059786","https://openalex.org/W2157009629","https://openalex.org/W3142089438","https://openalex.org/W4243891218","https://openalex.org/W6631637168"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2164493372","https://openalex.org/W2114980936","https://openalex.org/W2142405811","https://openalex.org/W1594445436","https://openalex.org/W2115513740","https://openalex.org/W4245595174","https://openalex.org/W2539511314","https://openalex.org/W2373135325"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"new":[3,60],"Built-In":[4],"Self-Test":[5],"(BIST)":[6],"schemes":[7,31,47],"for":[8,58,70],"fault":[9],"detection":[10],"and":[11,18,74],"diagnosis":[12,75],"of":[13,22,26,45,52,55,76,82,94],"Basic":[14],"Logic":[15],"Element":[16],"(BLE)":[17],"intra-cluster":[19],"(local)":[20],"interconnect":[21],"a":[23,71],"novel":[24],"mesh":[25],"cluster":[27],"FPGA.":[28,61],"The":[29,79],"proposed":[30],"avoid":[32],"redundant":[33],"test/diagnosis":[34,56],"configurations":[35,39,57,67],"by":[36],"merging":[37],"multiple":[38],"without":[40],"losing":[41],"diagnostic":[42],"resolution.":[43],"Efficiency":[44],"these":[46],"is":[48],"calculated":[49],"in":[50,87],"terms":[51],"respective":[53],"number":[54],"the":[59,77,90,95],"Results":[62],"show":[63],"that":[64],"50":[65],"BIST":[66],"are":[68,85],"required":[69],"complete":[72],"test":[73],"cluster.":[78],"testability":[80],"aspects":[81],"this":[83],"FPGA":[84,93],"explored":[86],"comparison":[88],"with":[89],"classic":[91],"clustered-mesh":[92],"same":[96],"parameters.":[97]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
