{"id":"https://openalex.org/W2007655096","doi":"https://doi.org/10.1109/dft.2012.6378210","title":"Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs","display_name":"Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W2007655096","doi":"https://doi.org/10.1109/dft.2012.6378210","mag":"2007655096"},"language":"en","primary_location":{"id":"doi:10.1109/dft.2012.6378210","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2012.6378210","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065265267","display_name":"Cinzia Bernardeschi","orcid":"https://orcid.org/0000-0003-1604-4465"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Cinzia Bernardeschi","raw_affiliation_strings":["Department of Information Engineering, University of Pisa, Italy","Dept. of Information Engineering, Univ. of Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dept. of Information Engineering, Univ. of Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007108808","display_name":"Luca Cassano","orcid":"https://orcid.org/0000-0003-3824-7714"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Cassano","raw_affiliation_strings":["Department of Information Engineering, University of Pisa, Italy","Dept. of Information Engineering, Univ. of Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dept. of Information Engineering, Univ. of Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090546515","display_name":"Andrea Domenici","orcid":"https://orcid.org/0000-0003-0685-2864"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Domenici","raw_affiliation_strings":["Department of Information Engineering, University of Pisa, Italy","Dept. of Information Engineering, Univ. of Pisa, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dept. of Information Engineering, Univ. of Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021426042","display_name":"Luca Sterpone","orcid":"https://orcid.org/0000-0002-3080-2560"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Sterpone","raw_affiliation_strings":["Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy","Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy#TAB#","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5065265267"],"corresponding_institution_ids":["https://openalex.org/I108290504"],"apc_list":null,"apc_paid":null,"fwci":2.4898,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.89648912,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"115","last_page":"120"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8871163725852966},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7539768218994141},{"id":"https://openalex.org/keywords/fault-injection","display_name":"Fault injection","score":0.7239623069763184},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6795463562011719},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6108396053314209},{"id":"https://openalex.org/keywords/aerospace","display_name":"Aerospace","score":0.5757049322128296},{"id":"https://openalex.org/keywords/automotive-industry","display_name":"Automotive industry","score":0.5262750387191772},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5049405694007874},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4831047058105469},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.46858566999435425},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.4166322946548462},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.362470805644989},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3383796215057373},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.24968302249908447},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19034436345100403},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.16833814978599548},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.11528074741363525}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8871163725852966},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7539768218994141},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.7239623069763184},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6795463562011719},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6108396053314209},{"id":"https://openalex.org/C167740415","wikidata":"https://www.wikidata.org/wiki/Q2876213","display_name":"Aerospace","level":2,"score":0.5757049322128296},{"id":"https://openalex.org/C526921623","wikidata":"https://www.wikidata.org/wiki/Q190117","display_name":"Automotive industry","level":2,"score":0.5262750387191772},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5049405694007874},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4831047058105469},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.46858566999435425},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.4166322946548462},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.362470805644989},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3383796215057373},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.24968302249908447},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19034436345100403},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.16833814978599548},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.11528074741363525},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/dft.2012.6378210","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2012.6378210","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},{"id":"pmh:oai:arpi.unipi.it:11568/195458","is_oa":false,"landing_page_url":"http://hdl.handle.net/11568/195458","pdf_url":null,"source":{"id":"https://openalex.org/S4377196265","display_name":"CINECA IRIS Institutial research information system (University of Pisa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I108290504","host_organization_name":"University of Pisa","host_organization_lineage":["https://openalex.org/I108290504"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:porto.polito.it:2508694","is_oa":false,"landing_page_url":"http://porto.polito.it/2508694/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1485650462","https://openalex.org/W2099479238","https://openalex.org/W2110254358","https://openalex.org/W2121451727","https://openalex.org/W2122512228","https://openalex.org/W2124618076","https://openalex.org/W2127501480","https://openalex.org/W2146816958","https://openalex.org/W2160685133","https://openalex.org/W2170171948","https://openalex.org/W2171823768","https://openalex.org/W2302574125","https://openalex.org/W2611031414","https://openalex.org/W6697858543","https://openalex.org/W6737664901"],"related_works":["https://openalex.org/W4225795411","https://openalex.org/W2809744190","https://openalex.org/W2511013388","https://openalex.org/W4392590355","https://openalex.org/W3021648695","https://openalex.org/W3006277082","https://openalex.org/W2610634993","https://openalex.org/W2081738003","https://openalex.org/W2097660413","https://openalex.org/W2943396510"],"abstract_inverted_index":{"SRAM-based":[0,61],"FPGAs":[1],"are":[2,106],"more":[3,5],"and":[4,77,108],"relevant":[6],"in":[7,56,92,117],"a":[8,100],"growing":[9],"number":[10],"of":[11,22,36,51,54,60,74,90,103,123,133],"applications,":[12],"ranging":[13],"from":[14],"the":[15,18,30,49,52,57,71,87,93,109,121,124,131,142],"automotive":[16],"to":[17,28,67,84,119],"aerospace":[19],"ones.":[20],"Designers":[21],"safety-critical":[23],"applications":[24],"demand":[25],"accurate":[26,45],"methodologies":[27],"evaluate":[29],"Single":[31],"Event":[32],"Upsets":[33],"(SEUs)":[34],"sensitivity":[35],"their":[37],"designs.":[38],"In":[39],"this":[40],"paper,":[41],"we":[42],"present":[43],"an":[44],"simulation":[46,137],"method":[47],"for":[48],"evaluation":[50],"effects":[53],"SEUs":[55,69,91],"configuration":[58,72,94],"memory":[59,73],"FPGAs.":[62],"The":[63,127],"approach":[64,135],"is":[65,82,115],"able":[66,83],"simulate":[68],"affecting":[70],"both":[75],"logic":[76],"routing":[78],"resources":[79],"since":[80,136],"it":[81],"accurately":[85],"model":[86],"electrical":[88],"behavior":[89],"memory.":[95],"Detailed":[96],"experimental":[97],"results":[98,128,138,143],"on":[99],"large":[101],"set":[102],"benchmark":[104],"circuits":[105],"provided":[107],"comparison":[110],"with":[111],"fault":[112,146],"injection":[113],"experiments":[114],"shown":[116],"order":[118],"validate":[120],"accuracy":[122],"proposed":[125],"method.":[126],"clearly":[129],"demonstrate":[130],"benefits":[132],"our":[134],"predict":[139],"almost":[140],"completely":[141],"obtained":[144],"through":[145],"injection.":[147]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":5},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":6}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}