{"id":"https://openalex.org/W2052950532","doi":"https://doi.org/10.1109/dft.2012.6378195","title":"Low pin count DfT technique for RFID ICs","display_name":"Low pin count DfT technique for RFID ICs","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W2052950532","doi":"https://doi.org/10.1109/dft.2012.6378195","mag":"2052950532"},"language":"en","primary_location":{"id":"doi:10.1109/dft.2012.6378195","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2012.6378195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013292385","display_name":"Marcelo Moraes","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Marcelo de Souza Moraes","raw_affiliation_strings":["CEITEC S.A., Porto Alegre, Rio Grande do Sul, Brazil","CEITEC S. A. Porto Alegre - RS - Brazil"],"affiliations":[{"raw_affiliation_string":"CEITEC S.A., Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":[]},{"raw_affiliation_string":"CEITEC S. A. Porto Alegre - RS - Brazil","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066941222","display_name":"Marcos Herv\u00e9","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Marcos Barcellos Herve","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul Escola de Engenharia, Porto Alegre, Rio Grande do Sul, Brazil","CEITEC S. A. Porto Alegre - RS - Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul Escola de Engenharia, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"CEITEC S. A. Porto Alegre - RS - Brazil","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5105973341","display_name":"Marcelo Lubaszewski","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Marcelo Soares Lubaszewski","raw_affiliation_strings":["Universidade Federal do Rio Grande do Sul Escola de Engenharia, Porto Alegre, Rio Grande do Sul, Brazil","CEITEC S. A. Porto Alegre - RS - Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Federal do Rio Grande do Sul Escola de Engenharia, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"CEITEC S. A. Porto Alegre - RS - Brazil","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5013292385"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2901,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.56651677,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"31","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.6611932516098022},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.6373553276062012},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6124957203865051},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5991260409355164},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.5751720666885376},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5647069215774536},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5537800788879395},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5216658115386963},{"id":"https://openalex.org/keywords/control-unit","display_name":"Control unit","score":0.4909837543964386},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.48510706424713135},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.47776567935943604},{"id":"https://openalex.org/keywords/test-method","display_name":"Test method","score":0.47177934646606445},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.46547338366508484},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4637366533279419},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.4393942356109619},{"id":"https://openalex.org/keywords/code-coverage","display_name":"Code coverage","score":0.4204064905643463},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.38585615158081055},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.35191965103149414},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.18270975351333618},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.14076873660087585},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1392812728881836}],"concepts":[{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.6611932516098022},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.6373553276062012},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6124957203865051},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5991260409355164},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.5751720666885376},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5647069215774536},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5537800788879395},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5216658115386963},{"id":"https://openalex.org/C81988521","wikidata":"https://www.wikidata.org/wiki/Q676838","display_name":"Control unit","level":2,"score":0.4909837543964386},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.48510706424713135},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.47776567935943604},{"id":"https://openalex.org/C132519959","wikidata":"https://www.wikidata.org/wiki/Q3077373","display_name":"Test method","level":2,"score":0.47177934646606445},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.46547338366508484},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4637366533279419},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.4393942356109619},{"id":"https://openalex.org/C53942775","wikidata":"https://www.wikidata.org/wiki/Q1211721","display_name":"Code coverage","level":3,"score":0.4204064905643463},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.38585615158081055},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.35191965103149414},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.18270975351333618},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.14076873660087585},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1392812728881836},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dft.2012.6378195","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dft.2012.6378195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1968890443","https://openalex.org/W2101177145","https://openalex.org/W2114265927","https://openalex.org/W2114584148","https://openalex.org/W2127184179","https://openalex.org/W2132110738","https://openalex.org/W2545004334"],"related_works":["https://openalex.org/W311918050","https://openalex.org/W2061326683","https://openalex.org/W4245311057","https://openalex.org/W2543176856","https://openalex.org/W2165948443","https://openalex.org/W2550015578","https://openalex.org/W2377850316","https://openalex.org/W2154529098","https://openalex.org/W2146381271","https://openalex.org/W2989178840"],"abstract_inverted_index":{"The":[0,19,71,124],"need":[1,46],"of":[2,26,29,37,47,66,95,99,126],"uniquely":[3],"identifiable":[4],"objects":[5],"for":[6,59,92],"multiple":[7],"applications":[8],"has":[9],"given":[10],"great":[11],"attention":[12],"to":[13,121],"RFID":[14,60],"ICs":[15,61],"over":[16],"the":[17,24,45,82,96,100,122,127],"years.":[18],"test":[20,77,104,112,117,128,137,140],"challenges":[21],"imposed":[22],"by":[23],"nature":[25],"this":[27,54],"type":[28],"IC":[30],"include":[31],"small":[32],"die":[33],"size,":[34],"reduced":[35],"number":[36],"external":[38,76],"pins,":[39],"low":[40,49],"power":[41],"mixed-signal":[42],"design":[43],"and":[44,87,102,115,139],"a":[48,56,116],"cost":[50],"production":[51],"test.":[52],"In":[53],"work,":[55],"DfT":[57],"technique":[58],"that":[62,81],"deals":[63],"with":[64],"some":[65],"these":[67],"limitations":[68],"is":[69,131],"presented.":[70],"method":[72,84],"requires":[73],"only":[74],"3":[75],"pins.":[78],"Results":[79],"show":[80],"proposed":[83],"allows":[85],"combining":[86],"managing":[88],"functional":[89],"tests":[90],"(used":[91],"testing":[93],"most":[94],"analog":[97],"parts":[98],"chip)":[101],"structural":[103],"(scan":[105],"test)":[106],"reaching":[107],"high":[108],"fault":[109],"coverage.":[110],"A":[111],"control":[113,129],"unit":[114,130],"wrapper":[118],"are":[119],"added":[120],"core.":[123],"architecture":[125],"presented":[132],"as":[133,135],"well":[134],"area,":[136],"coverage":[138],"time":[141],"results.":[142]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}