{"id":"https://openalex.org/W2965112795","doi":"https://doi.org/10.1109/dessert.2019.8770044","title":"Investigation and Design of a Threshold element for the Fault Self-Timed Circuits","display_name":"Investigation and Design of a Threshold element for the Fault Self-Timed Circuits","publication_year":2019,"publication_date":"2019-06-01","ids":{"openalex":"https://openalex.org/W2965112795","doi":"https://doi.org/10.1109/dessert.2019.8770044","mag":"2965112795"},"language":"en","primary_location":{"id":"doi:10.1109/dessert.2019.8770044","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dessert.2019.8770044","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 10th International Conference on Dependable Systems, Services and Technologies (DESSERT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113484795","display_name":"Anton N. Kamenskih","orcid":null},"institutions":[{"id":"https://openalex.org/I3123069486","display_name":"Perm National Research Polytechnic University","ror":"https://ror.org/05c0ns027","country_code":"RU","type":"education","lineage":["https://openalex.org/I3123069486"]}],"countries":["RU"],"is_corresponding":true,"raw_author_name":"Anton N. Kamenskih","raw_affiliation_strings":["Perm National Research Polytechnic University, Perm, Russia"],"affiliations":[{"raw_affiliation_string":"Perm National Research Polytechnic University, Perm, Russia","institution_ids":["https://openalex.org/I3123069486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084987875","display_name":"Sergey F. Tyurin","orcid":"https://orcid.org/0000-0002-5707-5404"},"institutions":[{"id":"https://openalex.org/I3123069486","display_name":"Perm National Research Polytechnic University","ror":"https://ror.org/05c0ns027","country_code":"RU","type":"education","lineage":["https://openalex.org/I3123069486"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Sergey F. Tyurin","raw_affiliation_strings":["Perm National Research Polytechnic University, Perm, Russia"],"affiliations":[{"raw_affiliation_string":"Perm National Research Polytechnic University, Perm, Russia","institution_ids":["https://openalex.org/I3123069486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5113484795"],"corresponding_institution_ids":["https://openalex.org/I3123069486"],"apc_list":null,"apc_paid":null,"fwci":0.1192,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.45388655,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"705","issue":null,"first_page":"29","last_page":"33"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7032414674758911},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7006544470787048},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6351864337921143},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6039968729019165},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4869295358657837},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.47451251745224},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.4670962691307068},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.45046892762184143},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.43104618787765503},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.41742199659347534},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38346949219703674},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.29082292318344116},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23006826639175415},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21564370393753052},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2149774432182312},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1618787944316864},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.14623162150382996},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08965680003166199},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.08157229423522949}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7032414674758911},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7006544470787048},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6351864337921143},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6039968729019165},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4869295358657837},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.47451251745224},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.4670962691307068},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.45046892762184143},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.43104618787765503},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.41742199659347534},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38346949219703674},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.29082292318344116},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23006826639175415},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21564370393753052},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2149774432182312},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1618787944316864},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.14623162150382996},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08965680003166199},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.08157229423522949},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dessert.2019.8770044","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dessert.2019.8770044","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 10th International Conference on Dependable Systems, Services and Technologies (DESSERT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1978207864","https://openalex.org/W1995341919","https://openalex.org/W2051934751","https://openalex.org/W2102871594","https://openalex.org/W2114683624","https://openalex.org/W2137458827","https://openalex.org/W2281947896","https://openalex.org/W2521635751","https://openalex.org/W2569065831","https://openalex.org/W2792893134","https://openalex.org/W2926260636","https://openalex.org/W3148985627","https://openalex.org/W7062389935"],"related_works":["https://openalex.org/W2153096481","https://openalex.org/W2148616436","https://openalex.org/W2102525122","https://openalex.org/W4245282135","https://openalex.org/W4306316843","https://openalex.org/W2130594209","https://openalex.org/W2036953450","https://openalex.org/W4300955944","https://openalex.org/W2170004886","https://openalex.org/W2527822502"],"abstract_inverted_index":{"G-flip-flops":[0],"are":[1,15,81],"the":[2,6,16,19,22,39,50,95,98,122,136,148,161,164],"important":[3],"elements":[4,31,46,87],"of":[5,21,35,41,73,112,124,160,163],"so-called":[7],"asynchronous":[8,139],"circuits":[9,71,117,142],"and":[10,38,76,116,140,151],"self-timed":[11,70,141],"circuits.":[12],"These":[13],"flip-flops":[14],"threshold":[17,30,40,45,91,145],"elements,":[18],"basis":[20],"neural":[23],"networks.":[24],"At":[25],"present,":[26],"analog-to-digital":[27],"converters":[28],"use":[29],"too.":[32],"The":[33,108,155],"number":[34],"inputs":[36],"n":[37,53,78],"operation":[42],"m":[43,74],"characterize":[44],"named":[47],"THmn.":[48],"In":[49],"event,":[51],"that":[52,88,143],"is":[54],"not":[55],"equal":[56],"to":[57,94,100,120,153],"m;":[58],"a":[59,90],"THmn":[60,113],"can":[61],"be":[62],"useful":[63],"in":[64,118],"fault-tolerant":[65],"systems.":[66],"For":[67],"example,":[68],"redundancy":[69],"consist":[72],"channels":[75],"only":[77],"from":[79],"them":[80],"workable.":[82],"However,":[83],"available":[84],"references":[85],"describe":[86],"have":[89,144],"for":[92,135,147],"transition":[93,114],"\"1\"":[96,150],"state,":[97],"return":[99],"zero":[101],"occurs":[102],"without":[103],"taking":[104],"into":[105],"account":[106],"failures.":[107],"paper":[109,156],"presents":[110],"investigation":[111],"functions":[115],"order":[119],"clarify":[121],"features":[123],"their":[125],"functioning.":[126],"Authors":[127],"proposes":[128],"new":[129],"element":[130],"-":[131],"hysteresis":[132],"flip-flop":[133],"3/4":[134],"fault":[137],"tolerant":[138],"both":[146],"set":[149],"returning":[152],"zero.":[154],"provides":[157],"an":[158],"assessment":[159],"effectiveness":[162],"proposed":[165],"device.":[166]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
