{"id":"https://openalex.org/W2947203440","doi":"https://doi.org/10.1109/ddecs.2019.8724662","title":"A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network","display_name":"A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network","publication_year":2019,"publication_date":"2019-04-01","ids":{"openalex":"https://openalex.org/W2947203440","doi":"https://doi.org/10.1109/ddecs.2019.8724662","mag":"2947203440"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2019.8724662","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2019.8724662","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038426994","display_name":"Sergei Odintsov","orcid":"https://orcid.org/0000-0001-9512-6017"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":true,"raw_author_name":"Sergei Odintsov","raw_affiliation_strings":["Dept. of Computer Systems, Tallinn Univ. of Technology, Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"Dept. of Computer Systems, Tallinn Univ. of Technology, Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091713814","display_name":"Ludovica Bozzoli","orcid":"https://orcid.org/0000-0001-5099-9359"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Ludovica Bozzoli","raw_affiliation_strings":["Computer and Control Engineering, Politecnico di Torino, Turin, Italy"],"affiliations":[{"raw_affiliation_string":"Computer and Control Engineering, Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018567565","display_name":"Corrado De Sio","orcid":"https://orcid.org/0000-0003-4212-3052"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Corrado De Sio","raw_affiliation_strings":["Computer and Control Engineering, Politecnico di Torino, Turin, Italy"],"affiliations":[{"raw_affiliation_string":"Computer and Control Engineering, Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021426042","display_name":"Luca Sterpone","orcid":"https://orcid.org/0000-0002-3080-2560"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Sterpone","raw_affiliation_strings":["Computer and Control Engineering, Politecnico di Torino, Turin, Italy"],"affiliations":[{"raw_affiliation_string":"Computer and Control Engineering, Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059021602","display_name":"Artur Jutman","orcid":"https://orcid.org/0000-0002-2018-5589"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Artur Jutman","raw_affiliation_strings":["Testonica Lab, Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"Testonica Lab, Tallinn, Estonia","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5038426994"],"corresponding_institution_ids":["https://openalex.org/I111112146"],"apc_list":null,"apc_paid":null,"fwci":0.4815,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.59339943,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6986855268478394},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.550160825252533},{"id":"https://openalex.org/keywords/printed-circuit-board","display_name":"Printed circuit board","score":0.4997375011444092},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4756205379962921},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46712714433670044},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4418392777442932},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4393683969974518},{"id":"https://openalex.org/keywords/spurious-relationship","display_name":"Spurious relationship","score":0.4196426272392273},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4143301248550415},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4079738259315491},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3221237361431122},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27886953949928284},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21159318089485168}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6986855268478394},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.550160825252533},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.4997375011444092},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4756205379962921},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46712714433670044},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4418392777442932},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4393683969974518},{"id":"https://openalex.org/C97256817","wikidata":"https://www.wikidata.org/wiki/Q1462316","display_name":"Spurious relationship","level":2,"score":0.4196426272392273},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4143301248550415},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4079738259315491},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3221237361431122},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27886953949928284},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21159318089485168},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2019.8724662","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2019.8724662","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1609593969","https://openalex.org/W1971688816","https://openalex.org/W1988707081","https://openalex.org/W2016977576","https://openalex.org/W2063146338","https://openalex.org/W2072330676","https://openalex.org/W2108172432","https://openalex.org/W2111122459","https://openalex.org/W2154446814","https://openalex.org/W2154749389","https://openalex.org/W2340344720","https://openalex.org/W2547800307","https://openalex.org/W2615189621","https://openalex.org/W2767016509","https://openalex.org/W2781720365","https://openalex.org/W2789286477","https://openalex.org/W2802572254"],"related_works":["https://openalex.org/W3113091479","https://openalex.org/W2162899405","https://openalex.org/W941090075","https://openalex.org/W2044987316","https://openalex.org/W3134374554","https://openalex.org/W2237480245","https://openalex.org/W2075065631","https://openalex.org/W2519167559","https://openalex.org/W4311248832","https://openalex.org/W4386113923"],"abstract_inverted_index":{"Nowadays,":[0],"increasing":[1,58],"demand":[2],"for":[3,17],"High-Performance":[4,88],"Systems":[5],"produces":[6],"significant":[7],"growth":[8],"in":[9,66,98,108,135],"usage":[10],"of":[11,27,43,64,70,87,178],"Field":[12],"Programmable":[13],"Gate":[14],"Arrays":[15],"(FPGAs)":[16],"different":[18],"applications":[19],"thanks":[20],"to":[21,83,131,168],"their":[22],"flexibility":[23],"and":[24,48,95,118,155,187],"high":[25],"level":[26],"parallelism.":[28],"Such":[29],"systems":[30],"rely":[31],"on":[32,143],"complex":[33],"multi-layer":[34],"Printed":[35],"Circuit":[36],"Board":[37],"Assemblies":[38],"(PCBA)with":[39],"a":[40,74,91,99,109,126,136,144],"few":[41],"dozens":[42],"hidden":[44],"layers,":[45],"stacked":[46],"microvias":[47],"high-density":[49],"interconnects.":[50],"Along":[51],"with":[52,77],"creating":[53],"new":[54,127],"test":[55],"challenges,":[56],"the":[57,62,114,170,176,179],"PCBA":[59,137],"complexity":[60],"elevates":[61],"criticality":[63],"defects":[65],"various":[67],"subsystems.":[68],"One":[69],"such":[71],"sub-systems":[72],"is":[73,141],"Power-Delivery-Network":[75],"(PDN)":[76],"operating":[78],"margin":[79],"progressively":[80],"reduced":[81],"due":[82],"increasingly":[84],"strict":[85],"requirements":[86],"applications.":[89],"As":[90],"consequence,":[92],"Marginal":[93,133],"Defects":[94,134],"process":[96],"variations":[97,154],"PDN":[100,153,162],"may":[101],"create":[102],"latent":[103],"problems":[104],"that":[105,147],"will":[106],"manifest":[107],"particular":[110],"condition":[111],"thus":[112,156],"compromising":[113],"overall":[115],"system":[116],"performance":[117],"causing":[119],"malfunctions.":[120],"In":[121],"this":[122],"paper":[123],"we":[124],"propose":[125],"FPGA-based":[128],"non-intrusive":[129],"method":[130,140],"detect":[132],"PDN.":[138],"The":[139],"based":[142],"monitoring":[145],"circuit":[146],"measures":[148],"signal":[149],"delays":[150],"caused":[151],"by":[152,184],"detects":[157],"relevant":[158],"anomalies.":[159],"Additional":[160],"ad-hoc":[161],"stress":[163,186],"circuits":[164],"have":[165],"been":[166],"developed":[167],"validate":[169],"measurement":[171],"technique.":[172],"Experimental":[173],"results":[174],"demonstrating":[175],"consistency":[177],"proposed":[180],"approach":[181],"are":[182],"obtained":[183],"comparing":[185],"non-stress":[188],"scenarios.":[189]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
