{"id":"https://openalex.org/W2620359275","doi":"https://doi.org/10.1109/ddecs.2017.7934577","title":"Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator","display_name":"Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W2620359275","doi":"https://doi.org/10.1109/ddecs.2017.7934577","mag":"2620359275"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2017.7934577","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2017.7934577","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061976867","display_name":"Madis Kerner","orcid":"https://orcid.org/0000-0002-8702-3592"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Madis Kerner","raw_affiliation_strings":["Dept. of Computer Systems, Tallinn University of Technology, Estonia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Systems, Tallinn University of Technology, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057936224","display_name":"Kalle Tammem\u00e4e","orcid":"https://orcid.org/0000-0003-4781-1364"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Kalle Tammemae","raw_affiliation_strings":["Dept. of Computer Systems, Tallinn University of Technology, Estonia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Systems, Tallinn University of Technology, Estonia","institution_ids":["https://openalex.org/I111112146"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I111112146"],"apc_list":null,"apc_paid":null,"fwci":0.5706,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.585692,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"10","issue":null,"first_page":"92","last_page":"95"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7949552536010742},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6052354574203491},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.4643894135951996},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.44248804450035095},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4372240900993347},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32200586795806885},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08687445521354675}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7949552536010742},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6052354574203491},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.4643894135951996},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.44248804450035095},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4372240900993347},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32200586795806885},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08687445521354675},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2017.7934577","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2017.7934577","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth","score":0.5199999809265137}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W66270334","https://openalex.org/W983829968","https://openalex.org/W1515653459","https://openalex.org/W1961566989","https://openalex.org/W2106069155","https://openalex.org/W2222971467","https://openalex.org/W4231980566","https://openalex.org/W4285719527","https://openalex.org/W6631016718","https://openalex.org/W6675746997","https://openalex.org/W6688889381"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W2029210135"],"abstract_inverted_index":{"Hierarchical":[0],"temporal":[1],"memory":[2],"(HTM)":[3],"is":[4,31,68,101],"the":[5,8,22,52,71,75,84,89,98],"model":[6],"of":[7,17,24,51,65,73,97],"neocortex":[9,26],"functionality,":[10,28],"developed":[11],"by":[12],"Numenta,":[13],"Inc.":[14],"The":[15,63,95],"level":[16],"implementation":[18,50],"does":[19],"cover":[20],"only":[21],"subset":[23],"actual":[25],"layers":[27],"but,":[29],"however,":[30],"sufficient":[32],"to":[33,69],"be":[34],"useful":[35],"in":[36],"different":[37],"domain":[38],"areas":[39],"e.g.":[40],"for":[41,54,88,123],"a":[42,60,119],"novelty":[43],"or":[44,56,79],"anomaly":[45],"detection.":[46],"Numenta":[47],"provides":[48],"their":[49],"HTM":[53,76],"commercial":[55],"research":[57],"purposes":[58],"as":[59,111,115,117],"software":[61],"solution.":[62],"purpose":[64],"this":[66],"work":[67],"investigate":[70],"feasibility":[72],"implementing":[74],"algorithm":[77],"partly":[78],"entirely":[80],"on":[81,103],"FPGA,":[82],"providing":[83],"suitable":[85],"building":[86],"block":[87],"resource":[90,104],"limited":[91],"cyber":[92],"physical":[93],"systems.":[94],"uniqueness":[96],"provided":[99],"solution":[100],"based":[102],"efficient":[105],"Linear":[106],"Feedback":[107],"Shift":[108],"Registers":[109],"(LFSR)":[110],"connection":[112],"address":[113],"generators,":[114],"well":[116],"using":[118],"simple":[120],"serial":[121],"interface":[122],"inter-column":[124],"communication.":[125]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}