{"id":"https://openalex.org/W2618741328","doi":"https://doi.org/10.1109/ddecs.2017.7934571","title":"Cycle-accurate software modeling for RTL verification of embedded systems","display_name":"Cycle-accurate software modeling for RTL verification of embedded systems","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W2618741328","doi":"https://doi.org/10.1109/ddecs.2017.7934571","mag":"2618741328"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2017.7934571","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2017.7934571","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033241617","display_name":"Michael Schwarz","orcid":"https://orcid.org/0000-0002-9828-0308"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Michael Schwarz","raw_affiliation_strings":["Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087718222","display_name":"Carlos Villarraga","orcid":"https://orcid.org/0000-0002-7699-8917"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Carlos Villarraga","raw_affiliation_strings":["Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047920654","display_name":"Dominik Stoffel","orcid":"https://orcid.org/0000-0002-8180-9738"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dominik Stoffel","raw_affiliation_strings":["Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066184879","display_name":"Wolfgang Kunz","orcid":"https://orcid.org/0000-0002-6612-2946"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfgang Kunz","raw_affiliation_strings":["Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical & Comp. Engineering, University of Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I153267046"],"apc_list":null,"apc_paid":null,"fwci":0.1902,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.33073323,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"103","last_page":"108"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/firmware","display_name":"Firmware","score":0.8805140256881714},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8045322299003601},{"id":"https://openalex.org/keywords/dependability","display_name":"Dependability","score":0.6879484057426453},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6408907175064087},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.42379823327064514},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33390673995018005},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18363738059997559},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1510097086429596},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.12262833118438721}],"concepts":[{"id":"https://openalex.org/C67212190","wikidata":"https://www.wikidata.org/wiki/Q104851","display_name":"Firmware","level":2,"score":0.8805140256881714},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8045322299003601},{"id":"https://openalex.org/C77019957","wikidata":"https://www.wikidata.org/wiki/Q2689057","display_name":"Dependability","level":2,"score":0.6879484057426453},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6408907175064087},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.42379823327064514},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33390673995018005},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18363738059997559},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1510097086429596},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.12262833118438721}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2017.7934571","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2017.7934571","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems (DDECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W39785869","https://openalex.org/W1865448657","https://openalex.org/W1998819749","https://openalex.org/W2027830835","https://openalex.org/W2045787134","https://openalex.org/W2076285066","https://openalex.org/W2082172430","https://openalex.org/W2107971662","https://openalex.org/W2143823357","https://openalex.org/W2159772935","https://openalex.org/W2295201563","https://openalex.org/W3151763762","https://openalex.org/W4213255380","https://openalex.org/W4250291977","https://openalex.org/W4254390804","https://openalex.org/W6657564345","https://openalex.org/W6683225327"],"related_works":["https://openalex.org/W4385624297","https://openalex.org/W1526521547","https://openalex.org/W2007388836","https://openalex.org/W4247881240","https://openalex.org/W3180981818","https://openalex.org/W2403824868","https://openalex.org/W4388023871","https://openalex.org/W2356515587","https://openalex.org/W2351580829","https://openalex.org/W2392099550"],"abstract_inverted_index":{"Today's":[0],"applications":[1,43],"for":[2,29,56],"HW/SW-systems,":[3],"such":[4,42],"as":[5],"the":[6,23,57,79,104,110],"Internet-of-Things,":[7],"often":[8],"demand":[9],"SoC":[10],"architectures":[11],"where":[12],"sophisticated":[13],"firmware":[14,108],"is":[15,67,82],"running":[16],"on":[17],"fairly":[18],"simple":[19],"processors.":[20],"Designers":[21],"face":[22],"challenge":[24],"of":[25,63,78,87,123],"meeting":[26],"high":[27],"requirements":[28],"these":[30],"systems":[31],"regarding":[32],"their":[33],"efficiency":[34],"and":[35,59,106],"dependability":[36],"under":[37],"severe":[38],"cost":[39],"constraints.":[40],"Targeting":[41],"this":[44],"paper":[45],"presents":[46],"a":[47,52,95],"new":[48],"technique":[49],"to":[50,93,131],"generate":[51,94],"joint":[53],"computational":[54,65],"model":[55,66,81,100],"hardware":[58],"its":[60,107],"firmware.":[61],"Generation":[62],"our":[64,88,132],"interleaved":[68],"with":[69],"techniques":[70],"from":[71],"WCET":[72],"analysis":[73],"so":[74],"that":[75,101],"clock-cycle":[76],"accuracy":[77],"resulting":[80],"achieved.":[83],"As":[84],"an":[85,118,121],"application":[86],"approach,":[89],"we":[90],"present":[91],"how":[92],"fast,":[96],"cycle-accurate":[97,128],"RTL":[98,111,129],"simulation":[99,130],"can":[102],"replace":[103],"processor":[105],"in":[109],"system":[112],"description.":[113],"Our":[114],"experimental":[115],"results":[116],"show":[117],"acceleration":[119],"by":[120],"order":[122],"magnitude":[124],"when":[125],"applying":[126],"standard":[127],"modified":[133],"design.":[134]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
