{"id":"https://openalex.org/W2617418626","doi":"https://doi.org/10.1109/ddecs.2017.7934568","title":"A scalable technique to identify true critical paths in sequential circuits","display_name":"A scalable technique to identify true critical paths in sequential circuits","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W2617418626","doi":"https://doi.org/10.1109/ddecs.2017.7934568","mag":"2617418626"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2017.7934568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2017.7934568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010536057","display_name":"Raimund Ubar","orcid":"https://orcid.org/0000-0001-8186-4385"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":true,"raw_author_name":"Raimund Ubar","raw_affiliation_strings":["Tallinn University of Technology, Tallinn, ESTONIA"],"affiliations":[{"raw_affiliation_string":"Tallinn University of Technology, Tallinn, ESTONIA","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072185940","display_name":"Sergei Kostin","orcid":null},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Sergei Kostin","raw_affiliation_strings":["Tallinn University of Technology, Tallinn, ESTONIA"],"affiliations":[{"raw_affiliation_string":"Tallinn University of Technology, Tallinn, ESTONIA","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059391257","display_name":"Maksim Jenihhin","orcid":"https://orcid.org/0000-0001-8165-9592"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Maksim Jenihhin","raw_affiliation_strings":["Tallinn University of Technology, Tallinn, ESTONIA"],"affiliations":[{"raw_affiliation_string":"Tallinn University of Technology, Tallinn, ESTONIA","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010286547","display_name":"Jaan Raik","orcid":"https://orcid.org/0000-0001-8113-020X"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Jaan Raik","raw_affiliation_strings":["Tallinn University of Technology, Tallinn, ESTONIA"],"affiliations":[{"raw_affiliation_string":"Tallinn University of Technology, Tallinn, ESTONIA","institution_ids":["https://openalex.org/I111112146"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5010536057"],"corresponding_institution_ids":["https://openalex.org/I111112146"],"apc_list":null,"apc_paid":null,"fwci":0.1433,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.48730565,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"7","issue":null,"first_page":"152","last_page":"157"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.8205901980400085},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.7100026607513428},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6988140344619751},{"id":"https://openalex.org/keywords/identification","display_name":"Identification (biology)","score":0.5933414697647095},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5301246047019958},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.52635657787323},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5068703293800354},{"id":"https://openalex.org/keywords/circuit-reliability","display_name":"Circuit reliability","score":0.49017199873924255},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4850822985172272},{"id":"https://openalex.org/keywords/negative-bias-temperature-instability","display_name":"Negative-bias temperature instability","score":0.45709672570228577},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.43339988589286804},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34936147928237915},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.343010276556015},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24971747398376465},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21099403500556946},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2010883390903473},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.19926995038986206},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.18819209933280945},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09206360578536987},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.08200481534004211}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.8205901980400085},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.7100026607513428},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6988140344619751},{"id":"https://openalex.org/C116834253","wikidata":"https://www.wikidata.org/wiki/Q2039217","display_name":"Identification (biology)","level":2,"score":0.5933414697647095},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5301246047019958},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.52635657787323},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5068703293800354},{"id":"https://openalex.org/C2778309119","wikidata":"https://www.wikidata.org/wiki/Q5121614","display_name":"Circuit reliability","level":4,"score":0.49017199873924255},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4850822985172272},{"id":"https://openalex.org/C557185","wikidata":"https://www.wikidata.org/wiki/Q6987194","display_name":"Negative-bias temperature instability","level":5,"score":0.45709672570228577},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.43339988589286804},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34936147928237915},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.343010276556015},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24971747398376465},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21099403500556946},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2010883390903473},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.19926995038986206},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.18819209933280945},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09206360578536987},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.08200481534004211},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C59822182","wikidata":"https://www.wikidata.org/wiki/Q441","display_name":"Botany","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2017.7934568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2017.7934568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1487689459","https://openalex.org/W1582522144","https://openalex.org/W1583304273","https://openalex.org/W1964078389","https://openalex.org/W2036824070","https://openalex.org/W2088115909","https://openalex.org/W2102729267","https://openalex.org/W2105407012","https://openalex.org/W2134869654","https://openalex.org/W2136045023","https://openalex.org/W2142908374","https://openalex.org/W2150754796","https://openalex.org/W2156306402","https://openalex.org/W2158805860","https://openalex.org/W2159373619","https://openalex.org/W2169913777","https://openalex.org/W2389387540","https://openalex.org/W3009317406","https://openalex.org/W3014325818","https://openalex.org/W4251213825","https://openalex.org/W4254271670","https://openalex.org/W6680222014"],"related_works":["https://openalex.org/W1970920853","https://openalex.org/W2099679924","https://openalex.org/W2738622559","https://openalex.org/W2158440114","https://openalex.org/W1977755957","https://openalex.org/W2012426329","https://openalex.org/W2115165828","https://openalex.org/W2126834173","https://openalex.org/W4233474994","https://openalex.org/W2156064231"],"abstract_inverted_index":{"The":[0,22,111,126],"recent":[1],"advancements":[2],"in":[3,52,84],"the":[4,10,30,97,118,134],"implementation":[5],"technologies":[6],"have":[7],"brought":[8],"to":[9,90,121],"front":[11],"a":[12,72],"wide":[13],"spectrum":[14],"of":[15,36,46,80,117,133],"new":[16],"defect":[17],"types":[18],"and":[19,33,87,131],"reliability":[20,54,92],"phenomena.":[21],"conventional":[23],"design":[24],"techniques":[25],"do":[26],"not":[27],"cope":[28],"with":[29],"integration":[31],"capacity":[32],"stringent":[34],"requirements":[35],"today's":[37],"nanometer":[38],"technology":[39],"nodes.":[40],"Timing-critical":[41],"paths":[42,83,98,124],"analysis":[43],"is":[44],"one":[45],"such":[47],"tasks.":[48],"It":[49],"has":[50],"applications":[51],"gate-level":[53,122],"analysis,":[55],"e.g.,":[56],"Bias":[57],"Temperature":[58],"Instability":[59],"(BTI)":[60],"induced":[61],"aging,":[62],"but":[63],"also":[64],"several":[65],"others.":[66],"In":[67],"this":[68],"paper,":[69],"we":[70],"propose":[71],"scalable":[73],"simulation":[74],"based":[75],"technique":[76,120],"for":[77,99],"explicit":[78],"identification":[79],"true":[81],"timing-critical":[82],"both":[85],"combinational":[86],"sequential":[88],"circuits":[89],"enable":[91],"mitigation":[93],"approaches,":[94],"like":[95],"deciding":[96],"delay":[100,104],"monitor":[101],"insertion,":[102],"resizing":[103],"critical":[105],"gates":[106],"or":[107],"applying":[108],"rejuvenation":[109],"stimuli.":[110],"paper":[112],"demonstrates":[113],"an":[114],"efficient":[115],"application":[116],"proposed":[119],"NBTI-critical":[123],"identification.":[125],"experimental":[127],"results":[128],"prove":[129],"feasibility":[130],"scalability":[132],"technique.":[135]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}