{"id":"https://openalex.org/W2619511468","doi":"https://doi.org/10.1109/ddecs.2017.7934560","title":"An efficient physical design of fully-testable BDD-based circuits","display_name":"An efficient physical design of fully-testable BDD-based circuits","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W2619511468","doi":"https://doi.org/10.1109/ddecs.2017.7934560","mag":"2619511468"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2017.7934560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2017.7934560","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015509778","display_name":"Andreas Rauchenecker","orcid":null},"institutions":[{"id":"https://openalex.org/I121883995","display_name":"Johannes Kepler University of Linz","ror":"https://ror.org/052r2xn60","country_code":"AT","type":"education","lineage":["https://openalex.org/I121883995"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Andreas Rauchenecker","raw_affiliation_strings":["Institute for Integrated Circuits, Johannes Kepler University, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Integrated Circuits, Johannes Kepler University, Austria","institution_ids":["https://openalex.org/I121883995"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004214923","display_name":"Robert Wille","orcid":"https://orcid.org/0000-0002-4993-7860"},"institutions":[{"id":"https://openalex.org/I121883995","display_name":"Johannes Kepler University of Linz","ror":"https://ror.org/052r2xn60","country_code":"AT","type":"education","lineage":["https://openalex.org/I121883995"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Robert Wille","raw_affiliation_strings":["Institute for Integrated Circuits, Johannes Kepler University, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Integrated Circuits, Johannes Kepler University, Austria","institution_ids":["https://openalex.org/I121883995"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I121883995"],"apc_list":null,"apc_paid":null,"fwci":0.1902,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.33117896,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"6","last_page":"11"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6267104148864746},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6136451959609985},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5918331146240234},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5797596573829651},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.5599253177642822},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4980170726776123},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.48568543791770935},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.457528680562973},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.43655166029930115},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42596617341041565},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.24010735750198364},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22008353471755981},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20943623781204224},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19553151726722717},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17501407861709595},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.12914809584617615},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09324303269386292}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6267104148864746},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6136451959609985},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5918331146240234},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5797596573829651},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.5599253177642822},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4980170726776123},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.48568543791770935},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.457528680562973},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.43655166029930115},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42596617341041565},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.24010735750198364},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22008353471755981},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20943623781204224},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19553151726722717},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17501407861709595},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.12914809584617615},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09324303269386292},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2017.7934560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2017.7934560","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1485027372","https://openalex.org/W1496641256","https://openalex.org/W1603046844","https://openalex.org/W2000787196","https://openalex.org/W2006097283","https://openalex.org/W2030029202","https://openalex.org/W2080267935","https://openalex.org/W2096785857","https://openalex.org/W2101900253","https://openalex.org/W2120634758","https://openalex.org/W2133489199","https://openalex.org/W2135955108","https://openalex.org/W2146907344","https://openalex.org/W2156423392","https://openalex.org/W2156566689","https://openalex.org/W2206061721","https://openalex.org/W2543792268","https://openalex.org/W3014325818","https://openalex.org/W3150268867","https://openalex.org/W4249515509","https://openalex.org/W6628927936","https://openalex.org/W6629585307","https://openalex.org/W6636071136","https://openalex.org/W6650739249"],"related_works":["https://openalex.org/W2050432237","https://openalex.org/W1547612600","https://openalex.org/W4248910437","https://openalex.org/W2157467310","https://openalex.org/W2987341420","https://openalex.org/W3006742635","https://openalex.org/W2978818660","https://openalex.org/W3003815297","https://openalex.org/W2980006224","https://openalex.org/W1580581797"],"abstract_inverted_index":{"For":[0],"the":[1,19,45,102,142],"manufacturing":[2],"test":[3,13],"of":[4,49,84,104,124,144],"ASICs,":[5],"it":[6],"is":[7,57],"important":[8],"to":[9,17,37,43,75,92,152],"reach":[10],"a":[11],"high":[12],"coverage":[14],"in":[15,154],"order":[16,36],"get":[18],"defect":[20],"level":[21],"as":[22,24],"low":[23],"possible.":[25],"However,":[26],"complex":[27],"digital":[28],"circuits":[29,46,72,109,148],"are":[30,87,150],"usually":[31],"not":[32,111],"fully":[33,145],"testable.":[34],"In":[35,116],"address":[38],"that,":[39],"previous":[40],"work":[41],"suggested":[42],"realize":[44],"by":[47],"means":[48],"Binary":[50],"Decisions":[51],"Diagrams":[52],"(BDDs).":[53],"Here,":[54],"each":[55],"node":[56],"implemented":[58],"using":[59],"multiplexer":[60],"gates":[61,86,126],"(MUX":[62],"gates)":[63],"which,":[64],"with":[65,73,90],"some":[66],"minor":[67],"additions,":[68],"yield":[69],"100%":[70,106],"testable":[71,146],"respect":[74,91],"stuck-at":[76],"and":[77],"path-delay":[78],"faults.":[79],"Unfortunately,":[80],"current":[81],"physical":[82],"implementations":[83],"MUX":[85,125],"rather":[88],"expensive":[89],"propagation":[93],"delay,":[94],"power":[95],"consumption,":[96],"or":[97],"transistor":[98,130],"count.":[99],"Hence,":[100],"despite":[101],"prospect":[103],"gaining":[105],"testability,":[107],"BDD-based":[108,147],"did":[110],"find":[112],"significant":[113],"attention":[114],"yet.":[115],"this":[117,139],"work,":[118],"we":[119],"propose":[120],"an":[121],"alternative":[122],"realization":[123,143],"based":[127],"on":[128],"pass":[129],"logic":[131],"which":[132,149],"addresses":[133],"these":[134],"drawbacks.":[135],"Experiments":[136],"show":[137],"that":[138],"allows":[140],"for":[141],"competitive":[151],"or,":[153],"many":[155],"cases,":[156],"even":[157],"better":[158],"than":[159],"state-of-the-art":[160],"realizations.":[161]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}