{"id":"https://openalex.org/W2418115660","doi":"https://doi.org/10.1109/ddecs.2016.7482456","title":"A general approach for comparing metastable behavior of digital CMOS gates","display_name":"A general approach for comparing metastable behavior of digital CMOS gates","publication_year":2016,"publication_date":"2016-04-01","ids":{"openalex":"https://openalex.org/W2418115660","doi":"https://doi.org/10.1109/ddecs.2016.7482456","mag":"2418115660"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2016.7482456","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2016.7482456","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040349556","display_name":"Thomas Polzer","orcid":null},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"Thomas Polzer","raw_affiliation_strings":["TU Wien, Institute of Computer Engineering, Vienna, Austria"],"affiliations":[{"raw_affiliation_string":"TU Wien, Institute of Computer Engineering, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006749662","display_name":"Andreas Steininger","orcid":"https://orcid.org/0000-0002-3847-1647"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Andreas Steininger","raw_affiliation_strings":["TU Wien, Institute of Computer Engineering, Vienna, Austria"],"affiliations":[{"raw_affiliation_string":"TU Wien, Institute of Computer Engineering, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5040349556"],"corresponding_institution_ids":["https://openalex.org/I145847075"],"apc_list":null,"apc_paid":null,"fwci":0.1838,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56082359,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/metastability","display_name":"Metastability","score":0.7375521659851074},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6430701613426208},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6388856172561646},{"id":"https://openalex.org/keywords/semaphore","display_name":"Semaphore","score":0.6323147416114807},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5216910243034363},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5185618996620178},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5165680646896362},{"id":"https://openalex.org/keywords/element","display_name":"Element (criminal law)","score":0.4899060130119324},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.4596076011657715},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4261317551136017},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38074254989624023},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3661936819553375},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.209090918302536},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.13618767261505127},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.126079261302948},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07940816879272461},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07349655032157898}],"concepts":[{"id":"https://openalex.org/C89464430","wikidata":"https://www.wikidata.org/wiki/Q849516","display_name":"Metastability","level":2,"score":0.7375521659851074},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6430701613426208},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6388856172561646},{"id":"https://openalex.org/C95203288","wikidata":"https://www.wikidata.org/wiki/Q221682","display_name":"Semaphore","level":2,"score":0.6323147416114807},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5216910243034363},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5185618996620178},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5165680646896362},{"id":"https://openalex.org/C200288055","wikidata":"https://www.wikidata.org/wiki/Q2621792","display_name":"Element (criminal law)","level":2,"score":0.4899060130119324},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.4596076011657715},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4261317551136017},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38074254989624023},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3661936819553375},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.209090918302536},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.13618767261505127},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.126079261302948},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07940816879272461},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07349655032157898},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2016.7482456","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2016.7482456","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Reduced inequalities","id":"https://metadata.un.org/sdg/10","score":0.8199999928474426}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1975638748","https://openalex.org/W2003389159","https://openalex.org/W2006835049","https://openalex.org/W2128223917","https://openalex.org/W2148339609","https://openalex.org/W2150872535","https://openalex.org/W2911717499","https://openalex.org/W4233171134","https://openalex.org/W6890102150"],"related_works":["https://openalex.org/W3003341543","https://openalex.org/W2049762404","https://openalex.org/W2390878321","https://openalex.org/W60162714","https://openalex.org/W1739793394","https://openalex.org/W1990738635","https://openalex.org/W2740134768","https://openalex.org/W4236786572","https://openalex.org/W1998777675","https://openalex.org/W2991739378"],"abstract_inverted_index":{"In":[0],"digital":[1],"CMOS":[2],"essentially":[3],"all":[4,69],"sequential":[5,77,174],"function":[6],"blocks":[7],"may":[8],"get":[9],"metastable":[10,43],"in":[11,33,83,120],"one":[12],"way":[13],"or":[14,94],"another,":[15],"when":[16,138],"provided":[17],"with":[18,85,148],"marginal":[19],"inputs.":[20],"Most":[21],"often":[22,46],"the":[23,30,39,49,57,90,95,109,125,128,132,149,154,185],"result":[24],"is":[25,45,104],"a":[26,34,64,100,162,171],"delayed":[27],"reaction":[28],"at":[29],"output,":[31],"which,":[32],"synchronous":[35,72],"design,":[36],"potentially":[37],"violates":[38],"timing":[40],"assumptions.":[41],"Therefore":[42,119],"behavior":[44],"characterized":[47],"by":[48],"Mean":[50],"Time":[51],"Between":[52],"Upset":[53],"(MTBU),":[54],"which":[55],"reflects":[56],"expected":[58],"interval":[59],"between":[60],"such":[61,88],"violations":[62],"on":[63,108],"statistical":[65],"base.":[66],"However,":[67],"not":[68,105],"designs":[70],"are":[71,75],"-":[73],"there":[74,112],"even":[76],"elements":[78],"specifically":[79],"intended":[80],"for":[81,141],"use":[82,126],"context":[84],"elastic":[86],"timing,":[87],"as":[89],"mutual":[91],"exclusion":[92],"element":[93],"Muller":[96,179],"C-element.":[97],"For":[98],"these":[99],"characterization":[101],"via":[102],"MTBU":[103,151],"useful;":[106],"but":[107],"other":[110],"hand":[111],"seem":[113],"to":[114,170],"be":[115],"no":[116],"reasonable":[117],"alternatives.":[118],"this":[121,142],"paper":[122],"we":[123,166,187],"propose":[124],"of":[127,164,173],"delay":[129],"graph":[130,152],"(over":[131],"relevant":[133],"quantity":[134],"that":[135],"causes":[136],"metastability":[137,155],"becoming":[139],"marginal)":[140],"purpose.":[143],"We":[144],"elaborate":[145],"its":[146],"correspondence":[147],"usual":[150],"and":[153,159,181,183],"parameters,":[156],"namely":[157],"tau":[158],"T0.":[160],"As":[161],"proof":[163],"concept":[165],"apply":[167],"our":[168],"strategy":[169],"set":[172],"elements,":[175],"like":[176],"D-latch,":[177],"RS-latch,":[178],"C-element":[180],"mutex":[182],"discuss":[184],"differences":[186],"identified.":[188]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}