{"id":"https://openalex.org/W2045386776","doi":"https://doi.org/10.1109/ddecs.2012.6219079","title":"A SBST strategy to test microprocessors' Branch Target Buffer","display_name":"A SBST strategy to test microprocessors' Branch Target Buffer","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2045386776","doi":"https://doi.org/10.1109/ddecs.2012.6219079","mag":"2045386776"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2012.6219079","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2012.6219079","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049430681","display_name":"Paolo Bernardi","orcid":"https://orcid.org/0000-0002-0985-9327"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Bernardi","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067849496","display_name":"L. Ciganda","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Ciganda","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035251234","display_name":"Michelangelo Grosso","orcid":"https://orcid.org/0000-0002-9726-0356"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Grosso","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009336869","display_name":"Ernesto S\u00e1nchez","orcid":"https://orcid.org/0000-0002-7042-295X"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"E. Sanchez","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY#TAB#","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058555274","display_name":"M. Sonza Reorda","orcid":"https://orcid.org/0000-0003-2899-7669"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Sonza Reorda","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Automatica e Informatica - Politecnico di Torino, ITALY#TAB#","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":1.1348,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.75532527,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"306","last_page":"311"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8258991241455078},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7350794672966003},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5157747268676758},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.46819978952407837},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4629007577896118},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.43275949358940125},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.42639249563217163},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.42581087350845337},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42181020975112915},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.23304706811904907},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.23214808106422424},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.14500147104263306},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08390504121780396}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8258991241455078},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7350794672966003},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5157747268676758},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.46819978952407837},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4629007577896118},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.43275949358940125},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.42639249563217163},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.42581087350845337},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42181020975112915},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.23304706811904907},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.23214808106422424},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.14500147104263306},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08390504121780396},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ddecs.2012.6219079","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2012.6219079","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"},{"id":"pmh:oai:porto.polito.it:2495978","is_oa":false,"landing_page_url":"http://porto.polito.it/2495978/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1736634110","https://openalex.org/W1982892691","https://openalex.org/W2058315483","https://openalex.org/W2101340408","https://openalex.org/W2135784215","https://openalex.org/W2162696040","https://openalex.org/W2162736794"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2164493372","https://openalex.org/W2114980936","https://openalex.org/W4249526199","https://openalex.org/W1594445436","https://openalex.org/W2128920253","https://openalex.org/W2142405811","https://openalex.org/W2164349885"],"abstract_inverted_index":{"A":[0],"Branch":[1],"Target":[2],"Buffer":[3],"(BTB)":[4],"is":[5,33,86,92,102],"a":[6,37,72,88,114],"mechanism":[7],"to":[8,14,35,42,63,74,97],"support":[9],"speculative":[10],"execution":[11],"in":[12,23],"order":[13],"overcome":[15],"the":[16,52,95,99,108],"performance":[17],"penalty":[18],"caused":[19],"by":[20],"branch":[21],"instructions":[22],"pipelined":[24],"microprocessors.":[25],"Being":[26],"an":[27],"intrinsically":[28],"fault":[29,39],"tolerant":[30],"unit,":[31],"it":[32],"hard":[34],"achieve":[36],"good":[38],"coverage":[40],"resorting":[41],"plain":[43],"functional":[44,56],"testing":[45],"methods.":[46],"In":[47,68],"this":[48],"paper":[49],"we":[50,70],"analyze":[51],"causes":[53],"for":[54],"low":[55],"testability":[57],"and":[58,94,105],"propose":[59],"some":[60],"techniques":[61],"able":[62],"effectively":[64],"face":[65],"these":[66],"issues.":[67],"particular,":[69],"describe":[71],"strategy":[73,96],"perform":[75],"SBST":[76],"on":[77,113],"fully":[78],"associative":[79],"BTB":[80],"units.":[81],"The":[82],"unit's":[83],"general":[84],"structure":[85],"analyzed,":[87],"suitable":[89],"test":[90,100],"program":[91],"proposed":[93,109],"observe":[98],"responses":[101],"explained.":[103],"Feasibility":[104],"effectiveness":[106],"of":[107],"approach":[110],"are":[111],"shown":[112],"MIPS-like":[115],"processor.":[116]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}