{"id":"https://openalex.org/W2062795256","doi":"https://doi.org/10.1109/ddecs.2012.6219034","title":"Automatic integration of hardware descriptions into system-level models","display_name":"Automatic integration of hardware descriptions into system-level models","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2062795256","doi":"https://doi.org/10.1109/ddecs.2012.6219034","mag":"2062795256"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2012.6219034","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2012.6219034","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091155269","display_name":"Ralph G\u00f6rgen","orcid":null},"institutions":[{"id":"https://openalex.org/I202367325","display_name":"Oldenburger Institut f\u00fcr Informatik","ror":"https://ror.org/003sav189","country_code":"DE","type":"facility","lineage":["https://openalex.org/I202367325"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ralph Gorgen","raw_affiliation_strings":["OFFIS Institute of Information Technology, Oldenburg, Germany","OFFIS - Institute for Information Technology, 26121 Oldenburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"OFFIS Institute of Information Technology, Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]},{"raw_affiliation_string":"OFFIS - Institute for Information Technology, 26121 Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037107680","display_name":"Jan-Hendrik Oetjens","orcid":null},"institutions":[{"id":"https://openalex.org/I889804353","display_name":"Robert Bosch (Germany)","ror":"https://ror.org/01fe0jt45","country_code":"DE","type":"company","lineage":["https://openalex.org/I889804353"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jan-Hendrik Oetjens","raw_affiliation_strings":["Robert Bosch GmbH, Reutlingen, Germany","Robert Bosch GmbH, 72762 Reutlingen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Robert Bosch GmbH, Reutlingen, Germany","institution_ids":["https://openalex.org/I889804353"]},{"raw_affiliation_string":"Robert Bosch GmbH, 72762 Reutlingen, Germany","institution_ids":["https://openalex.org/I889804353"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048688572","display_name":"Wolfgang Nebel","orcid":null},"institutions":[{"id":"https://openalex.org/I129877168","display_name":"Carl von Ossietzky Universit\u00e4t Oldenburg","ror":"https://ror.org/033n9gh91","country_code":"DE","type":"education","lineage":["https://openalex.org/I129877168"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Wolfgang Nebel","raw_affiliation_strings":["Carl von Ossietzky University\uc2a0of\uc2a0Oldenburg, Oldenburg, Germany","Carl von Ossietzky University, 26111 Oldenburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carl von Ossietzky University\uc2a0of\uc2a0Oldenburg, Oldenburg, Germany","institution_ids":["https://openalex.org/I129877168"]},{"raw_affiliation_string":"Carl von Ossietzky University, 26111 Oldenburg, Germany","institution_ids":["https://openalex.org/I129877168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"105","last_page":"110"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8779665231704712},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8073754906654358},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7947031855583191},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.6472876071929932},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.6322956681251526},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5440194010734558},{"id":"https://openalex.org/keywords/transformation","display_name":"Transformation (genetics)","score":0.5066874623298645},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.45587462186813354},{"id":"https://openalex.org/keywords/readability","display_name":"Readability","score":0.4410073459148407},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.407428503036499},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4020376205444336},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.33609479665756226},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.29463398456573486}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8779665231704712},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8073754906654358},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7947031855583191},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.6472876071929932},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6322956681251526},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5440194010734558},{"id":"https://openalex.org/C204241405","wikidata":"https://www.wikidata.org/wiki/Q461499","display_name":"Transformation (genetics)","level":3,"score":0.5066874623298645},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.45587462186813354},{"id":"https://openalex.org/C2778143727","wikidata":"https://www.wikidata.org/wiki/Q1820650","display_name":"Readability","level":2,"score":0.4410073459148407},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.407428503036499},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4020376205444336},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.33609479665756226},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.29463398456573486},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2012.6219034","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2012.6219034","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321114","display_name":"Bundesministerium f\u00fcr Bildung und Forschung","ror":"https://ror.org/04pz7b180"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1512776169","https://openalex.org/W2104183572","https://openalex.org/W2117227842","https://openalex.org/W2138343703"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1984090905","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W4233602124","https://openalex.org/W2548456620","https://openalex.org/W2156965212","https://openalex.org/W2075214143","https://openalex.org/W1988777083"],"abstract_inverted_index":{"In":[0,50,67],"this":[1],"paper,":[2],"we":[3],"present":[4],"a":[5,20,25,72,77,89,100],"flow":[6],"for":[7],"integrating":[8],"hardware":[9,26,114],"descriptions":[10],"into":[11],"Simulink":[12,21,101],"simulations.":[13],"It":[14],"enables":[15],"the":[16,45,57,62,94,97],"automatic":[17],"generation":[18],"of":[19,24,61,96],"component":[22,27,98],"out":[23],"model":[28,47,64],"given":[29],"as":[30,76],"RT":[31],"level":[32],"VHDL.":[33],"The":[34,41,85],"approach":[35,70],"is":[36,65,83],"based":[37],"on":[38],"two":[39,110],"steps.":[40],"first":[42],"step":[43,87],"transforms":[44],"VHDL":[46],"to":[48,52,92],"SystemC.":[49],"contrast":[51],"existing":[53],"VHDL-to-SystemC":[54],"transformation":[55,104],"tools,":[56],"readability":[58],"and":[59],"configurability":[60],"input":[63],"preserved.":[66],"addition,":[68],"our":[69],"yields":[71],"more":[73],"exact":[74],"model,":[75],"custom":[78],"designed":[79],"VHDL-like":[80],"data-type":[81],"system":[82],"employed.":[84],"second":[86],"generates":[88],"specific":[90],"wrapper":[91],"allow":[93],"use":[95],"in":[99],"simulation.":[102],"This":[103],"strategy":[105],"will":[106],"be":[107],"evaluated":[108],"with":[109],"industrial":[111],"automotive":[112],"electronics":[113],"designs.":[115]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}