{"id":"https://openalex.org/W2118029394","doi":"https://doi.org/10.1109/ddecs.2011.5783119","title":"Advanced fault tolerant bus for multicore system implemented in FPGA","display_name":"Advanced fault tolerant bus for multicore system implemented in FPGA","publication_year":2011,"publication_date":"2011-04-01","ids":{"openalex":"https://openalex.org/W2118029394","doi":"https://doi.org/10.1109/ddecs.2011.5783119","mag":"2118029394"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2011.5783119","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2011.5783119","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083343772","display_name":"Martin Straka","orcid":"https://orcid.org/0000-0002-2207-0160"},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Martin Straka","raw_affiliation_strings":["Brno University of Technology, Brno, Czech Republic","Brno University of Technology, Bozetechova 2, 612 66, Czech Republic"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]},{"raw_affiliation_string":"Brno University of Technology, Bozetechova 2, 612 66, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045187923","display_name":"Jan Kastil","orcid":"https://orcid.org/0009-0007-2327-3270"},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Jan Kastil","raw_affiliation_strings":["Brno University of Technology, Brno, Czech Republic","Brno University of Technology, Bozetechova 2, 612 66, Czech Republic"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]},{"raw_affiliation_string":"Brno University of Technology, Bozetechova 2, 612 66, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103546959","display_name":"Jaroslav Novotny","orcid":null},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Jaroslav Novotny","raw_affiliation_strings":["Brno University of Technology, Brno, Czech Republic","Brno University of Technology, Bozetechova 2, 612 66, Czech Republic"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]},{"raw_affiliation_string":"Brno University of Technology, Bozetechova 2, 612 66, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040514508","display_name":"Zden\u011bk Kot\u00e1sek","orcid":null},"institutions":[{"id":"https://openalex.org/I60587646","display_name":"Brno University of Technology","ror":"https://ror.org/03613d656","country_code":"CZ","type":"education","lineage":["https://openalex.org/I60587646"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Zdenek Kotasek","raw_affiliation_strings":["Brno University of Technology, Brno, Czech Republic","Brno University of Technology, Bozetechova 2, 612 66, Czech Republic"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Brno University of Technology, Brno, Czech Republic","institution_ids":["https://openalex.org/I60587646"]},{"raw_affiliation_string":"Brno University of Technology, Bozetechova 2, 612 66, Czech Republic","institution_ids":["https://openalex.org/I60587646"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8109,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.77096115,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"397","last_page":"398"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.741729736328125},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7113611698150635},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6997671723365784},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6975356340408325},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.6703332662582397},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6179927587509155},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6176389455795288},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6047059893608093},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5958983898162842},{"id":"https://openalex.org/keywords/replication","display_name":"Replication (statistics)","score":0.5617438554763794},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.427871972322464},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37381958961486816},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.24571320414543152},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22082895040512085},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2173946499824524}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.741729736328125},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7113611698150635},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6997671723365784},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6975356340408325},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.6703332662582397},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6179927587509155},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6176389455795288},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6047059893608093},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5958983898162842},{"id":"https://openalex.org/C12590798","wikidata":"https://www.wikidata.org/wiki/Q3933199","display_name":"Replication (statistics)","level":2,"score":0.5617438554763794},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.427871972322464},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37381958961486816},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.24571320414543152},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22082895040512085},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2173946499824524},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2011.5783119","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2011.5783119","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321006","display_name":"Grantov\u00e1 Agentura \u010cesk\u00e9 Republiky","ror":"https://ror.org/01pv73b02"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2053188356","https://openalex.org/W2086054919","https://openalex.org/W2119747227","https://openalex.org/W2129223399","https://openalex.org/W2133678523","https://openalex.org/W2160011949","https://openalex.org/W2171311711","https://openalex.org/W6678078822"],"related_works":["https://openalex.org/W2186949690","https://openalex.org/W2167303720","https://openalex.org/W2133682266","https://openalex.org/W2154109900","https://openalex.org/W2497617944","https://openalex.org/W3019064768","https://openalex.org/W1563139915","https://openalex.org/W2109715593","https://openalex.org/W2061075966","https://openalex.org/W3019683061"],"abstract_inverted_index":{"In":[0],"the":[1,20,24,42,47,67,80],"paper,":[2],"a":[3],"technique":[4],"for":[5],"design":[6],"of":[7,19,26,46,70],"highly":[8],"dependable":[9],"communication":[10],"structure":[11,25],"in":[12],"SRAM-based":[13],"FPGA":[14],"is":[15],"presented.":[16],"The":[17,35,56],"architecture":[18],"multicore":[21],"system":[22,62],"and":[23,44,82],"fault":[27,36],"tolerant":[28,37],"bus":[29],"with":[30,52],"cache":[31],"memories":[32],"are":[33,39,73],"demonstrated.":[34],"properties":[38],"achieved":[40],"by":[41],"replication":[43],"utilization":[45],"self":[48],"checking":[49],"techniques":[50],"together":[51],"partial":[53],"dynamic":[54],"reconfiguration.":[55],"experimental":[57],"results":[58],"show":[59],"that":[60],"presented":[61],"has":[63],"small":[64],"overhead":[65],"if":[66],"high":[68],"number":[69],"function":[71],"units":[72],"used.":[74],"All":[75],"experiments":[76],"were":[77],"done":[78],"on":[79],"Virtex5":[81],"Virtex6":[83],"platform.":[84]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}