{"id":"https://openalex.org/W2125156433","doi":"https://doi.org/10.1109/ddecs.2011.5783082","title":"Implementation of Selective Fault Tolerance with conventional synthesis tools","display_name":"Implementation of Selective Fault Tolerance with conventional synthesis tools","publication_year":2011,"publication_date":"2011-04-01","ids":{"openalex":"https://openalex.org/W2125156433","doi":"https://doi.org/10.1109/ddecs.2011.5783082","mag":"2125156433"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2011.5783082","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2011.5783082","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068639653","display_name":"Michael Augustin","orcid":"https://orcid.org/0000-0001-9154-4051"},"institutions":[{"id":"https://openalex.org/I51783024","display_name":"Brandenburg University of Technology Cottbus-Senftenberg","ror":"https://ror.org/02wxx3e24","country_code":"DE","type":"education","lineage":["https://openalex.org/I51783024"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Michael Augustin","raw_affiliation_strings":["Computer Science Institute, BTU Cottbus, Cottbus, Germany","BTU Cottbus, Computer Science Institute, Erich-Weinert-Stra\u00dfe 1, 03046, Germany"],"affiliations":[{"raw_affiliation_string":"Computer Science Institute, BTU Cottbus, Cottbus, Germany","institution_ids":["https://openalex.org/I51783024"]},{"raw_affiliation_string":"BTU Cottbus, Computer Science Institute, Erich-Weinert-Stra\u00dfe 1, 03046, Germany","institution_ids":["https://openalex.org/I51783024"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020082098","display_name":"Michael G\u00f6ssel","orcid":null},"institutions":[{"id":"https://openalex.org/I176453806","display_name":"University of Potsdam","ror":"https://ror.org/03bnmw459","country_code":"DE","type":"education","lineage":["https://openalex.org/I176453806"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Michael Gossel","raw_affiliation_strings":["Computer Science Institute, Potsdam University, Potsdam, Germany","Potsdam University, Computer Science Institute, August-Bebel-Stra\u00dfe 89, 14482, Germany"],"affiliations":[{"raw_affiliation_string":"Computer Science Institute, Potsdam University, Potsdam, Germany","institution_ids":["https://openalex.org/I176453806"]},{"raw_affiliation_string":"Potsdam University, Computer Science Institute, August-Bebel-Stra\u00dfe 89, 14482, Germany","institution_ids":["https://openalex.org/I176453806"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111617436","display_name":"Rolf Kraemer","orcid":null},"institutions":[{"id":"https://openalex.org/I92894754","display_name":"Innovations for High Performance Microelectronics","ror":"https://ror.org/0489gab80","country_code":"DE","type":"facility","lineage":["https://openalex.org/I315704651","https://openalex.org/I92894754"]},{"id":"https://openalex.org/I4210159354","display_name":"Institut f\u00fcr Solartechnologien (Germany)","ror":"https://ror.org/0529ecj14","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210159354"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rolf Kraemer","raw_affiliation_strings":["IHP, Frankfurt, Germany","IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany"],"affiliations":[{"raw_affiliation_string":"IHP, Frankfurt, Germany","institution_ids":["https://openalex.org/I92894754"]},{"raw_affiliation_string":"IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany","institution_ids":["https://openalex.org/I4210159354"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5068639653"],"corresponding_institution_ids":["https://openalex.org/I51783024"],"apc_list":null,"apc_paid":null,"fwci":1.3248,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.83064595,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"213","last_page":"218"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.8392064571380615},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.8047953844070435},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6981381177902222},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.6606811881065369},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5574724078178406},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4995768070220947},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4768696427345276},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4559633433818817},{"id":"https://openalex.org/keywords/software-fault-tolerance","display_name":"Software fault tolerance","score":0.44610869884490967},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37504905462265015},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3720204830169678},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.33644795417785645},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1721193790435791},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.14844858646392822}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.8392064571380615},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.8047953844070435},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6981381177902222},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.6606811881065369},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5574724078178406},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4995768070220947},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4768696427345276},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4559633433818817},{"id":"https://openalex.org/C50712370","wikidata":"https://www.wikidata.org/wiki/Q4269346","display_name":"Software fault tolerance","level":3,"score":0.44610869884490967},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37504905462265015},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3720204830169678},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.33644795417785645},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1721193790435791},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.14844858646392822},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2011.5783082","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2011.5783082","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1500893261","https://openalex.org/W1548975601","https://openalex.org/W1559343931","https://openalex.org/W1821730155","https://openalex.org/W1870528983","https://openalex.org/W2000379092","https://openalex.org/W2025474944","https://openalex.org/W2099569658","https://openalex.org/W2105761964","https://openalex.org/W2112269194","https://openalex.org/W2154509298","https://openalex.org/W2340143290","https://openalex.org/W2489146530","https://openalex.org/W3149410719"],"related_works":["https://openalex.org/W2971479921","https://openalex.org/W3145923041","https://openalex.org/W2946906624","https://openalex.org/W841176518","https://openalex.org/W2157727563","https://openalex.org/W2101077206","https://openalex.org/W2024212764","https://openalex.org/W2470343202","https://openalex.org/W1978919910","https://openalex.org/W2098626762"],"abstract_inverted_index":{"Circuits":[0],"implementing":[1],"the":[2,28,53,58,73,96],"concept":[3],"of":[4,16,30,46,64,76],"Selective":[5,31],"Fault":[6,32],"Tolerance":[7,33],"according":[8],"to":[9,26,35,51,72],"are":[10],"fault-tolerant":[11],"for":[12],"a":[13,21,61,77,93],"specified":[14],"subset":[15],"inputs.":[17],"In":[18],"this":[19],"paper,":[20],"new":[22],"heuristic":[23,39],"is":[24,70,81],"presented":[25],"make":[27],"method":[29],"applicable":[34],"industrial":[36],"designs.":[37],"The":[38],"can":[40],"be":[41],"efficiently":[42],"implemented":[43],"by":[44,83],"use":[45],"conventional":[47],"design":[48],"tools.":[49],"Compared":[50],"TMR,":[52],"method,":[54],"in":[55,90],"combination":[56],"with":[57,95],"heuristic,":[59],"saves":[60],"huge":[62],"amount":[63],"area":[65],"redundancy":[66],"and":[67,92],"fault":[68],"tolerance":[69],"adapted":[71],"real":[74],"requirements":[75],"system":[78],"specification.":[79],"This":[80],"demonstrated":[82],"experimental":[84],"results":[85],"obtained":[86],"from":[87],"circuit":[88],"descriptions":[89],"Verilog":[91],"synthesis":[94],"tool":[97],"Synopsys.":[98]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
