{"id":"https://openalex.org/W2113827996","doi":"https://doi.org/10.1109/ddecs.2010.5491778","title":"NoGap<sup>CL</sup>: A flexible common language for processor hardware description","display_name":"NoGap<sup>CL</sup>: A flexible common language for processor hardware description","publication_year":2010,"publication_date":"2010-04-01","ids":{"openalex":"https://openalex.org/W2113827996","doi":"https://doi.org/10.1109/ddecs.2010.5491778","mag":"2113827996"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2010.5491778","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2010.5491778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100909012","display_name":"Wenbiao Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Wenbiao Zhou","raw_affiliation_strings":["Department of EE, Link\u00f6ping University, Linkoping, Sweden","[Department of EE, Link\u00f6ping university, Link\u00f6ping]"],"affiliations":[{"raw_affiliation_string":"Department of EE, Link\u00f6ping University, Linkoping, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"[Department of EE, Link\u00f6ping university, Link\u00f6ping]","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028995651","display_name":"Per Karlstr\u00f6m","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Per Karlstrom","raw_affiliation_strings":["Department of EE, Link\u00f6ping University, Linkoping, Sweden","[Department of EE, Link\u00f6ping university, Link\u00f6ping]"],"affiliations":[{"raw_affiliation_string":"Department of EE, Link\u00f6ping University, Linkoping, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"[Department of EE, Link\u00f6ping university, Link\u00f6ping]","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011014977","display_name":"Dake Liu","orcid":"https://orcid.org/0000-0002-4644-4892"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Dake Liu","raw_affiliation_strings":["Department of EE, Link\u00f6ping University, Linkoping, Sweden","[Department of EE, Link\u00f6ping university, Link\u00f6ping]"],"affiliations":[{"raw_affiliation_string":"Department of EE, Link\u00f6ping University, Linkoping, Sweden","institution_ids":["https://openalex.org/I102134673"]},{"raw_affiliation_string":"[Department of EE, Link\u00f6ping university, Link\u00f6ping]","institution_ids":["https://openalex.org/I102134673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100909012"],"corresponding_institution_ids":["https://openalex.org/I102134673"],"apc_list":null,"apc_paid":null,"fwci":0.9987,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.78211429,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"225","last_page":"228"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7660471200942993},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6996966600418091},{"id":"https://openalex.org/keywords/application-specific-instruction-set-processor","display_name":"Application-specific instruction-set processor","score":0.67596036195755},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5623520612716675},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.5510032773017883},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.5401220917701721},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5056664943695068},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4645170271396637},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45762383937835693},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44989627599716187},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.42802560329437256},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.4246959984302521},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.41958409547805786},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.41947096586227417},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.41899266839027405},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.16156736016273499}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7660471200942993},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6996966600418091},{"id":"https://openalex.org/C201736964","wikidata":"https://www.wikidata.org/wiki/Q621583","display_name":"Application-specific instruction-set processor","level":3,"score":0.67596036195755},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5623520612716675},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.5510032773017883},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.5401220917701721},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5056664943695068},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4645170271396637},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45762383937835693},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44989627599716187},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.42802560329437256},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.4246959984302521},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.41958409547805786},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.41947096586227417},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.41899266839027405},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.16156736016273499},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2010.5491778","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2010.5491778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1532503506","https://openalex.org/W1612189975","https://openalex.org/W1822615232","https://openalex.org/W1954375898","https://openalex.org/W2010074783","https://openalex.org/W2048490215","https://openalex.org/W2107168664","https://openalex.org/W2112537029","https://openalex.org/W2542693654","https://openalex.org/W4230144752","https://openalex.org/W4234669735","https://openalex.org/W6811785195","https://openalex.org/W6962873186"],"related_works":["https://openalex.org/W2036206036","https://openalex.org/W182515070","https://openalex.org/W2993622674","https://openalex.org/W4387540511","https://openalex.org/W2104586137","https://openalex.org/W4309639889","https://openalex.org/W4367172762","https://openalex.org/W1480407846","https://openalex.org/W4388344772","https://openalex.org/W2026197855"],"abstract_inverted_index":{"Flexible":[0],"Application":[1],"Specific":[2],"Instruction":[3],"set":[4],"Processors":[5],"(ASIP)":[6],"are":[7],"starting":[8],"to":[9,60,145],"replace":[10],"monolithic":[11],"ASICs":[12],"in":[13,137,161],"a":[14,29,42,84,91,116,140,162],"wide":[15],"variety":[16],"of":[17,22,36,53,57,103],"fields.":[18],"However":[19],"the":[20,54,74,104],"construction":[21],"an":[23,146],"ASIP":[24,45],"is":[25,41,67,89],"today":[26],"associated":[27],"with":[28,135],"substantial":[30],"design":[31,78,106],"effort.":[32],"NoGap":[33,58,69,80,99,111,128,136],"(Novel":[34],"Generator":[35],"Micro":[37],"Architecture":[38],"and":[39,76,88,143],"Processor)":[40],"tool":[43],"for":[44,64,120],"designs,":[46],"utilizing":[47],"hardware":[48,122],"multiplexed":[49],"data":[50,92],"paths.":[51],"One":[52],"main":[55],"advantages":[56],"compared":[59],"other":[61],"EDA":[62],"tools":[63],"processor":[65,86,121,126,154],"design,":[66],"that":[68],"impose":[70],"few":[71],"limits":[72],"on":[73],"architecture":[75],"thus":[77],"freedom.":[79],"does":[81],"not":[82,90],"assume":[83],"fixed":[85],"template":[87],"flow":[93],"synthesizer.":[94],"To":[95],"reach":[96],"this":[97,153],"flexibility":[98],"makes":[100],"heavy":[101],"use":[102],"compositional":[105],"principle.":[107],"This":[108],"paper":[109],"describe":[110],"<sup":[112,129],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[113,130],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">CL</sup>":[114,131],",":[115],"flexible":[117],"common":[118],"language":[119],"description.":[123],"A":[124],"RISC":[125],"using":[127],"has":[132],"been":[133],"constructed":[134],"less":[138],"than":[139],"working":[141],"day":[142],"synthesized":[144],"FPGA.":[147],"With":[148],"no":[149],"FPGA":[150],"specific":[151],"optimizations":[152],"met":[155],"timing":[156],"closure":[157],"at":[158],"178":[159],"MHz":[160],"Virtex-4":[163],"LX80":[164],"speedgrade":[165],"12.":[166]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}