{"id":"https://openalex.org/W2082418834","doi":"https://doi.org/10.1109/ddecs.2010.5491763","title":"A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks","display_name":"A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks","publication_year":2010,"publication_date":"2010-04-01","ids":{"openalex":"https://openalex.org/W2082418834","doi":"https://doi.org/10.1109/ddecs.2010.5491763","mag":"2082418834"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2010.5491763","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2010.5491763","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051320260","display_name":"Farid Lahrach","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I140494188","display_name":"Universit\u00e9 de Technologie de Troyes","ror":"https://ror.org/01qhqcj41","country_code":"FR","type":"education","lineage":["https://openalex.org/I140494188"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Farid Lahrach","raw_affiliation_strings":["Institute Charles Delaunay (ICD), STMR, UMR CNRS 6279, Laboratoire de mod\u00e9lisation et S\u00fbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes, Troyes, France","Institue Charles Delaunay (ICD), STMR, UMR CNRS 6279. Laboratoire de mod\u00e9lisation et S\u00dbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes (UTT), 12, rue Marie-Curie, 10010, Troyes Cedex, France"],"affiliations":[{"raw_affiliation_string":"Institute Charles Delaunay (ICD), STMR, UMR CNRS 6279, Laboratoire de mod\u00e9lisation et S\u00fbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes, Troyes, France","institution_ids":["https://openalex.org/I140494188","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"Institue Charles Delaunay (ICD), STMR, UMR CNRS 6279. Laboratoire de mod\u00e9lisation et S\u00dbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes (UTT), 12, rue Marie-Curie, 10010, Troyes Cedex, France","institution_ids":["https://openalex.org/I140494188","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013158965","display_name":"Abderrazek Abdaoui","orcid":null},"institutions":[{"id":"https://openalex.org/I140494188","display_name":"Universit\u00e9 de Technologie de Troyes","ror":"https://ror.org/01qhqcj41","country_code":"FR","type":"education","lineage":["https://openalex.org/I140494188"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Abderrazek Abdaoui","raw_affiliation_strings":["Institute Charles Delaunay (ICD), STMR, UMR CNRS 6279, Laboratoire de mod\u00e9lisation et S\u00fbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes, Troyes, France","Institue Charles Delaunay (ICD), STMR, UMR CNRS 6279. Laboratoire de mod\u00e9lisation et S\u00dbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes (UTT), 12, rue Marie-Curie, 10010, Troyes Cedex, France"],"affiliations":[{"raw_affiliation_string":"Institute Charles Delaunay (ICD), STMR, UMR CNRS 6279, Laboratoire de mod\u00e9lisation et S\u00fbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes, Troyes, France","institution_ids":["https://openalex.org/I140494188","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"Institue Charles Delaunay (ICD), STMR, UMR CNRS 6279. Laboratoire de mod\u00e9lisation et S\u00dbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes (UTT), 12, rue Marie-Curie, 10010, Troyes Cedex, France","institution_ids":["https://openalex.org/I140494188","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080909127","display_name":"Abderrahim Doumar","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I140494188","display_name":"Universit\u00e9 de Technologie de Troyes","ror":"https://ror.org/01qhqcj41","country_code":"FR","type":"education","lineage":["https://openalex.org/I140494188"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Abderrahim Doumar","raw_affiliation_strings":["Institute Charles Delaunay (ICD), STMR, UMR CNRS 6279, Laboratoire de mod\u00e9lisation et S\u00fbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes, Troyes, France","Institue Charles Delaunay (ICD), STMR, UMR CNRS 6279. Laboratoire de mod\u00e9lisation et S\u00dbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes (UTT), 12, rue Marie-Curie, 10010, Troyes Cedex, France"],"affiliations":[{"raw_affiliation_string":"Institute Charles Delaunay (ICD), STMR, UMR CNRS 6279, Laboratoire de mod\u00e9lisation et S\u00fbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes, Troyes, France","institution_ids":["https://openalex.org/I140494188","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"Institue Charles Delaunay (ICD), STMR, UMR CNRS 6279. Laboratoire de mod\u00e9lisation et S\u00dbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes (UTT), 12, rue Marie-Curie, 10010, Troyes Cedex, France","institution_ids":["https://openalex.org/I140494188","https://openalex.org/I1294671590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103186279","display_name":"\u0116ric Ch\u00e2telet","orcid":"https://orcid.org/0000-0001-5859-9480"},"institutions":[{"id":"https://openalex.org/I140494188","display_name":"Universit\u00e9 de Technologie de Troyes","ror":"https://ror.org/01qhqcj41","country_code":"FR","type":"education","lineage":["https://openalex.org/I140494188"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Eric Chatelet","raw_affiliation_strings":["Institute Charles Delaunay (ICD), STMR, UMR CNRS 6279, Laboratoire de mod\u00e9lisation et S\u00fbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes, Troyes, France","Institue Charles Delaunay (ICD), STMR, UMR CNRS 6279. Laboratoire de mod\u00e9lisation et S\u00dbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes (UTT), 12, rue Marie-Curie, 10010, Troyes Cedex, France"],"affiliations":[{"raw_affiliation_string":"Institute Charles Delaunay (ICD), STMR, UMR CNRS 6279, Laboratoire de mod\u00e9lisation et S\u00fbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes, Troyes, France","institution_ids":["https://openalex.org/I140494188","https://openalex.org/I1294671590"]},{"raw_affiliation_string":"Institue Charles Delaunay (ICD), STMR, UMR CNRS 6279. Laboratoire de mod\u00e9lisation et S\u00dbret\u00e9 des Syst\u00e8mes (LM2S), Universit\u00e9 de Technologie de Troyes (UTT), 12, rue Marie-Curie, 10010, Troyes Cedex, France","institution_ids":["https://openalex.org/I140494188","https://openalex.org/I1294671590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5051320260"],"corresponding_institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I140494188"],"apc_list":null,"apc_paid":null,"fwci":1.8057161,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.87498358,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"305","last_page":"308"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.7567321062088013},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7144089937210083},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6902451515197754},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6890643835067749},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6888906359672546},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.6774889826774597},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6647845506668091},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6074105501174927},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.49345532059669495},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4754069447517395},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47133708000183105},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.45917797088623047},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4319608807563782},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33453893661499023},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30091607570648193},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.15357705950737},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06864455342292786}],"concepts":[{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.7567321062088013},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7144089937210083},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6902451515197754},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6890643835067749},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6888906359672546},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.6774889826774597},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6647845506668091},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6074105501174927},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.49345532059669495},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4754069447517395},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47133708000183105},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.45917797088623047},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4319608807563782},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33453893661499023},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30091607570648193},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.15357705950737},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06864455342292786},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ddecs.2010.5491763","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2010.5491763","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-02563086v1","is_oa":false,"landing_page_url":"https://utt.hal.science/hal-02563086","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2010, Vienna, Austria. pp.305-308, ⟨10.1109/DDECS.2010.5491763⟩","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1547465446","https://openalex.org/W1576549492","https://openalex.org/W1832437964","https://openalex.org/W2072159791","https://openalex.org/W2105120486","https://openalex.org/W2110864115","https://openalex.org/W2119841103","https://openalex.org/W2128755437","https://openalex.org/W2135225513","https://openalex.org/W2143470198","https://openalex.org/W2150629048","https://openalex.org/W2151954769","https://openalex.org/W2156547554","https://openalex.org/W2162447939","https://openalex.org/W3142089438","https://openalex.org/W6682859328"],"related_works":["https://openalex.org/W2130594209","https://openalex.org/W1950809481","https://openalex.org/W2000379092","https://openalex.org/W2085988155","https://openalex.org/W2152497502","https://openalex.org/W2085138612","https://openalex.org/W2184926577","https://openalex.org/W2316937124","https://openalex.org/W3184123971","https://openalex.org/W2040421909"],"abstract_inverted_index":{"International":[0],"audience":[1]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}