{"id":"https://openalex.org/W2113139456","doi":"https://doi.org/10.1109/ddecs.2009.5012141","title":"An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs","display_name":"An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs","publication_year":2009,"publication_date":"2009-04-01","ids":{"openalex":"https://openalex.org/W2113139456","doi":"https://doi.org/10.1109/ddecs.2009.5012141","mag":"2113139456"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2009.5012141","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012141","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067849496","display_name":"L. Ciganda","orcid":null},"institutions":[{"id":"https://openalex.org/I180910786","display_name":"Universidad de la Rep\u00fablica","ror":"https://ror.org/030bbe882","country_code":"UY","type":"education","lineage":["https://openalex.org/I180910786"]}],"countries":["UY"],"is_corresponding":true,"raw_author_name":"L. Ciganda","raw_affiliation_strings":["Universidad de la Republica Uruguay, Montevideo, Uruguay"],"affiliations":[{"raw_affiliation_string":"Universidad de la Republica Uruguay, Montevideo, Uruguay","institution_ids":["https://openalex.org/I180910786"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002649650","display_name":"Francesco Abate","orcid":"https://orcid.org/0000-0002-5665-1828"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Abate","raw_affiliation_strings":["Politecnico di Torino, Italy","Politecnico di Torino, (Italy)"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, (Italy)","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049430681","display_name":"Paolo Bernardi","orcid":"https://orcid.org/0000-0002-0985-9327"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"P. Bernardi","raw_affiliation_strings":["Politecnico di Torino, Italy","Politecnico di Torino, (Italy)"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, (Italy)","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088353376","display_name":"Massimo Bruno","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Bruno","raw_affiliation_strings":["Politecnico di Torino, Italy","Politecnico di Torino, (Italy)"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, (Italy)","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058555274","display_name":"M. Sonza Reorda","orcid":"https://orcid.org/0000-0003-2899-7669"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Sonza Reorda","raw_affiliation_strings":["Politecnico di Torino, Italy","Politecnico di Torino, (Italy)"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Politecnico di Torino, (Italy)","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5067849496"],"corresponding_institution_ids":["https://openalex.org/I180910786"],"apc_list":null,"apc_paid":null,"fwci":1.6066,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.84202062,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"258","last_page":"263"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7043627500534058},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6921858191490173},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6096760034561157},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5891183614730835},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.546035647392273},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.48408567905426025},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.42226219177246094},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.4138139486312866},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.35427772998809814},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.34760957956314087},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.339141845703125}],"concepts":[{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7043627500534058},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6921858191490173},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6096760034561157},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5891183614730835},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.546035647392273},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.48408567905426025},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.42226219177246094},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.4138139486312866},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.35427772998809814},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.34760957956314087},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.339141845703125},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/ddecs.2009.5012141","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012141","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:porto.polito.it:2260996","is_oa":false,"landing_page_url":"http://porto.polito.it/2260996/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:porto.polito.it:2374278","is_oa":false,"landing_page_url":"http://porto.polito.it/2374278/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5600000023841858,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1543263356","https://openalex.org/W2075996757","https://openalex.org/W2107522943","https://openalex.org/W2122955150","https://openalex.org/W2133803721","https://openalex.org/W2134702967","https://openalex.org/W2135627440","https://openalex.org/W2171452343","https://openalex.org/W3140757238","https://openalex.org/W3142218480"],"related_works":["https://openalex.org/W2157191248","https://openalex.org/W2107525390","https://openalex.org/W2150046587","https://openalex.org/W2164493372","https://openalex.org/W2114980936","https://openalex.org/W4249526199","https://openalex.org/W1594445436","https://openalex.org/W4245595174","https://openalex.org/W2115513740","https://openalex.org/W2539511314"],"abstract_inverted_index":{"Reducing":[0],"the":[1,12,15,28,42,50,58,72,79,86,89,94,98,102],"cost":[2,13],"of":[3,14,45,53,60,76,88,96],"test":[4,87,99,113],"(in":[5],"particular":[6],"by":[7,31],"reducing":[8],"its":[9],"duration":[10],"and":[11,49,82,92,108],"required":[16],"ATE)":[17],"is":[18],"a":[19,105],"common":[20,74],"goal":[21],"which":[22],"has":[23],"largely":[24],"been":[25],"pursued":[26],"in":[27,104],"past,":[29],"mainly":[30],"introducing":[32],"suitable":[33],"on":[34,101],"chip":[35],"Design":[36],"for":[37,85],"Testability":[38],"(DfT)":[39],"circuitry.":[40],"Today,":[41],"increasing":[43],"popularity":[44],"sophisticated":[46],"DfT":[47],"architectures":[48],"parallel":[51],"emergence":[52],"new":[54],"ATE":[55],"families":[56],"allow":[57],"identification":[59],"innovative":[61],"solutions":[62],"effectively":[63],"facing":[64],"that":[65],"goal.":[66],"In":[67],"this":[68],"paper":[69],"we":[70],"face":[71],"increasingly":[73],"situation":[75],"SoCs":[77],"adopting":[78],"IEEE":[80],"1149.1":[81],"1500":[83],"standards":[84],"internal":[90],"cores,":[91],"explore":[93],"idea":[95],"storing":[97],"program":[100],"tester":[103],"compressed":[106],"form,":[107],"decompressing":[109],"it":[110],"on-the-fly":[111],"during":[112],"application.":[114]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
