{"id":"https://openalex.org/W2162432958","doi":"https://doi.org/10.1109/ddecs.2009.5012114","title":"Structural test of programmed FPGA circuits","display_name":"Structural test of programmed FPGA circuits","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W2162432958","doi":"https://doi.org/10.1109/ddecs.2009.5012114","mag":"2162432958"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2009.5012114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066149539","display_name":"Martin Rozkovec","orcid":"https://orcid.org/0000-0001-5221-616X"},"institutions":[{"id":"https://openalex.org/I147009085","display_name":"Technical University of Liberec","ror":"https://ror.org/02jtk7k02","country_code":"CZ","type":"education","lineage":["https://openalex.org/I147009085"]}],"countries":["CZ"],"is_corresponding":true,"raw_author_name":"Martin Rozkovec","raw_affiliation_strings":["Institute of Information technologies and electronics, Faculty of Mechatronics, Technical University of Liberec, Liberec, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Institute of Information technologies and electronics, Faculty of Mechatronics, Technical University of Liberec, Liberec, Czech Republic","institution_ids":["https://openalex.org/I147009085"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101706960","display_name":"Ond\u0159ej Nov\u00e1k","orcid":"https://orcid.org/0000-0002-3030-0616"},"institutions":[{"id":"https://openalex.org/I147009085","display_name":"Technical University of Liberec","ror":"https://ror.org/02jtk7k02","country_code":"CZ","type":"education","lineage":["https://openalex.org/I147009085"]}],"countries":["CZ"],"is_corresponding":false,"raw_author_name":"Ondrej Novak","raw_affiliation_strings":["Institute of Information technologies and electronics, Faculty of Mechatronics, Technical University of Liberec, Liberec, Czech Republic"],"affiliations":[{"raw_affiliation_string":"Institute of Information technologies and electronics, Faculty of Mechatronics, Technical University of Liberec, Liberec, Czech Republic","institution_ids":["https://openalex.org/I147009085"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5066149539"],"corresponding_institution_ids":["https://openalex.org/I147009085"],"apc_list":null,"apc_paid":null,"fwci":1.0553,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.79595461,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"136","last_page":"139"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.785175085067749},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7773911356925964},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7722873687744141},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6831053495407104},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.5540512800216675},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5287137627601624},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5207212567329407},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.499828577041626},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4885648190975189},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44498634338378906},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.4304143190383911},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4049844443798065},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38710010051727295},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18256738781929016},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0890214741230011},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06262773275375366}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.785175085067749},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7773911356925964},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7722873687744141},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6831053495407104},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.5540512800216675},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5287137627601624},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5207212567329407},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.499828577041626},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4885648190975189},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44498634338378906},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4304143190383911},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4049844443798065},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38710010051727295},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18256738781929016},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0890214741230011},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06262773275375366},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2009.5012114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W53227076","https://openalex.org/W1544497049","https://openalex.org/W1826425057","https://openalex.org/W1921192440","https://openalex.org/W2054149682"],"related_works":["https://openalex.org/W2170314243","https://openalex.org/W2119179026","https://openalex.org/W2794947590","https://openalex.org/W2114971758","https://openalex.org/W2109932036","https://openalex.org/W2093081283","https://openalex.org/W3209275736","https://openalex.org/W1544420370","https://openalex.org/W2999380228","https://openalex.org/W2148089379"],"abstract_inverted_index":{"We":[0,58],"present":[1,59],"a":[2,66],"new":[3],"concept":[4],"of":[5,13,19,29,46,62,80],"the":[6,20,22,30,71,75],"test":[7,18,51,81],"method":[8,23,40],"for":[9,55],"FPGA":[10,72],"devices.":[11],"Instead":[12],"being":[14],"focused":[15],"on":[16,43,84],"structural":[17],"device,":[21],"tests":[24],"logic":[25],"and":[26,49,65],"interconnection":[27],"resources":[28],"FPGA,":[31],"that":[32,69],"are":[33,88],"actually":[34],"used":[35],"by":[36],"implemented":[37],"circuit.":[38],"The":[39],"is":[41],"based":[42],"reconfiguration":[44],"ability":[45],"nowadays":[47],"FPGAs":[48],"utilizes":[50],"vectors":[52],"originally":[53],"created":[54],"ASIC":[56,76],"circuits.":[57],"an":[60],"idea":[61],"circuit":[63],"partitioning":[64],"transcription":[67],"scheme,":[68],"converts":[70],"netlist":[73],"to":[74],"one.":[77],"Preliminary":[78],"results":[79],"patterns":[82],"efficiency":[83],"transformed":[85],"benchmark":[86],"circuits":[87],"presented.":[89]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
