{"id":"https://openalex.org/W2112434965","doi":"https://doi.org/10.1109/ddecs.2009.5012099","title":"Self-timed full adder designs based on hybrid input encoding","display_name":"Self-timed full adder designs based on hybrid input encoding","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W2112434965","doi":"https://doi.org/10.1109/ddecs.2009.5012099","mag":"2112434965"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2009.5012099","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012099","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112390368","display_name":"P. Balasubramanian","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"P. Balasubramanian","raw_affiliation_strings":["School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, United Kingdom#TAB#"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, United Kingdom#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108435403","display_name":"D. Edwards","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"D.A. Edwards","raw_affiliation_strings":["School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, United Kingdom#TAB#"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, United Kingdom#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046793634","display_name":"Charlie Brej","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"C. Brej","raw_affiliation_strings":["School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, United Kingdom#TAB#"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of Manchester, Institute of Science and Technology, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, United Kingdom#TAB#","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5112390368"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.1369142,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"56","last_page":"61"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9433730840682983},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7658722400665283},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7356342077255249},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.6593624949455261},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.5505889654159546},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4878723621368408},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.48597654700279236},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.4700055718421936},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4281068444252014},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3334754705429077},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32828375697135925},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3260073661804199},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.16649124026298523},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1413474977016449},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0755133330821991},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07442259788513184}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9433730840682983},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7658722400665283},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7356342077255249},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.6593624949455261},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.5505889654159546},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4878723621368408},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48597654700279236},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.4700055718421936},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4281068444252014},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3334754705429077},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32828375697135925},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3260073661804199},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.16649124026298523},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1413474977016449},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0755133330821991},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07442259788513184},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/ddecs.2009.5012099","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2009.5012099","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits &amp; Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.603.9103","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.603.9103","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://brej.org/papers/ddecs_bala.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.671.4972","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.671.4972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://apt.cs.manchester.ac.uk/ftp/pub/apt/papers/Auth_PB_DDECS09.pdf","raw_type":"text"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/6cb92759-ee3f-498b-824c-c8e43cc5784a","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/6cb92759-ee3f-498b-824c-c8e43cc5784a","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Balasubramanian, P, Edwards, D A & Brej, C 2009, Self-timed full adder designs based on hybrid input encoding. in Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009|Proc. IEEE Symp. Des. Diagn. Electron. Circuits Syst., DDECS. IEEE Computer Society , pp. 56-61, 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, Liberec, 1/07/09. https://doi.org/10.1109/DDECS.2009.5012099","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.atira.dk:publications/6cb92759-ee3f-498b-824c-c8e43cc5784a","is_oa":false,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/selftimed-full-adder-designs-based-on-hybrid-input-encoding(6cb92759-ee3f-498b-824c-c8e43cc5784a).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Balasubramanian, P, Edwards, D A & Brej, C 2009, Self-timed full adder designs based on hybrid input encoding. in Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009|Proc. IEEE Symp. Des. Diagn. Electron. Circuits Syst., DDECS. IEEE Computer Society , pp. 56-61, 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, Liberec, 1/07/09. https://doi.org/10.1109/DDECS.2009.5012099","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G661603445","display_name":null,"funder_award_id":"EP/D052238/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1522009072","https://openalex.org/W1535891768","https://openalex.org/W1999082644","https://openalex.org/W2052771421","https://openalex.org/W2102346142","https://openalex.org/W2117299791","https://openalex.org/W2127220676","https://openalex.org/W2134829921","https://openalex.org/W2147779504","https://openalex.org/W2540271382","https://openalex.org/W6631409759","https://openalex.org/W6679370083"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2516396101","https://openalex.org/W2953746839","https://openalex.org/W2370097872","https://openalex.org/W2112595260","https://openalex.org/W4295540194","https://openalex.org/W986131379","https://openalex.org/W1993041309"],"abstract_inverted_index":{"Self-timed":[0],"full":[1,53],"adder":[2,31,54],"designs":[3,32,55],"based":[4],"on":[5],"commercial":[6],"synchronous":[7],"resources":[8],"(standard":[9],"cells),":[10],"constructed":[11],"using":[12],"a":[13,59,93],"mix":[14],"of":[15,29,90],"complete":[16],"delay-insensitive":[17,63],"codes":[18],"adopted":[19],"for":[20,66],"inputs":[21,69],"are":[22],"described":[23],"in":[24,88],"this":[25],"paper.":[26],"While":[27],"one":[28],"the":[30,36,38,68,84],"incorporates":[33],"redundancy":[34,82],"into":[35,83],"logic,":[37],"other":[39],"design":[40],"does":[41],"not.":[42],"Comparisons":[43],"have":[44],"been":[45,74],"carried":[46],"out":[47,76],"with":[48,100],"respect":[49,101],"to":[50,97,102],"various":[51],"self-timed":[52],"which":[56],"employ":[57],"only":[58],"single":[60],"widely":[61],"used":[62],"input":[64],"encoding":[65],"both":[67],"and":[70,104],"outputs.":[71],"It":[72],"has":[73],"found":[75],"from":[77],"exhaustive":[78],"simulations":[79],"that":[80],"incorporating":[81],"logic":[85],"actually":[86],"benefits":[87],"terms":[89],"delay,":[91],"but":[92],"non-redundant":[94],"implementation":[95],"proves":[96],"be":[98],"beneficial":[99],"power":[103],"area":[105],"parameters.":[106]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
