{"id":"https://openalex.org/W2112561944","doi":"https://doi.org/10.1109/ddecs.2008.4538809","title":"A Cost Effective BIST Second-Order \u00bf-\u00bf Modulator","display_name":"A Cost Effective BIST Second-Order \u00bf-\u00bf Modulator","publication_year":2008,"publication_date":"2008-04-01","ids":{"openalex":"https://openalex.org/W2112561944","doi":"https://doi.org/10.1109/ddecs.2008.4538809","mag":"2112561944"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2008.4538809","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2008.4538809","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108047268","display_name":"Hao-Chiao Hong","orcid":"https://orcid.org/0000-0003-0757-1001"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Hao-Chiao Hong","raw_affiliation_strings":["Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","[Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu]","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075115401","display_name":"Sheng-Chuan Liang","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Sheng-Chuan Liang","raw_affiliation_strings":["Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","[Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu]","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061003986","display_name":"Hong-Chin Song","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hong-Chin Song","raw_affiliation_strings":["Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","[Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"[Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu]","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5108047268"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.2422,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.62463705,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.7938454151153564},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.6125546097755432},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5659576058387756},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5570288896560669},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.52996426820755},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4990088939666748},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4840211570262909},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.430084228515625},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4246911108493805},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3865431845188141},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3586958944797516},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2675935626029968},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.122550368309021}],"concepts":[{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.7938454151153564},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.6125546097755432},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5659576058387756},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5570288896560669},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.52996426820755},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4990088939666748},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4840211570262909},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.430084228515625},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4246911108493805},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3865431845188141},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3586958944797516},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2675935626029968},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.122550368309021},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2008.4538809","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2008.4538809","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1503450335","https://openalex.org/W1516585181","https://openalex.org/W1979300943","https://openalex.org/W2071628448","https://openalex.org/W2078335310","https://openalex.org/W2084128131","https://openalex.org/W2102634163","https://openalex.org/W2124912253","https://openalex.org/W2136100286","https://openalex.org/W2147292717","https://openalex.org/W2158254213","https://openalex.org/W2545945801","https://openalex.org/W4239972799","https://openalex.org/W6679945778"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2142405811","https://openalex.org/W2114980936","https://openalex.org/W2164493372","https://openalex.org/W1594445436","https://openalex.org/W4245595174","https://openalex.org/W2115513740","https://openalex.org/W2539511314"],"abstract_inverted_index":{"This":[0],"paper":[1],"demonstrates":[2],"a":[3,18,25,79],"cost":[4],"effective":[5],"built-in-":[6],"self-test":[7],"(BIST)":[8],"\u03a3-\u0394":[9,21],"modulator":[10,22],"prototype.":[11],"The":[12,33,97],"BIST":[13,31,34,76,99,121],"prototype":[14,77],"is":[15,36,88],"composed":[16],"of":[17,84,104,112],"design-for-digital-testability":[19],"second-order":[20],"chip":[23],"and":[24,68,109],"FPGA":[26],"which":[27,87,116],"implements":[28],"the":[29,39,49,75,94,102,110,114],"digital":[30],"functions.":[32],"system":[35],"based":[37],"on":[38],"modified":[40],"control":[41],"sine":[42],"wave":[43],"fitting":[44],"(MCSWF)":[45],"procedure.":[46],"Different":[47],"from":[48],"conventional":[50],"analysis":[51],"method":[52],"using":[53],"Fast":[54],"Fourier":[55],"Transform":[56],"(FFT),":[57],"this":[58],"implementation":[59,100],"requires":[60],"neither":[61],"any":[62],"parallel":[63],"multiplier":[64],"nor":[65],"complex":[66],"CPU/DSP":[67],"bulky":[69],"memory.":[70],"Measurement":[71],"results":[72],"show":[73],"that":[74],"gives":[78],"signal-to-noise-and-distortion":[80],"ratio":[81],"(SNDR)":[82],"result":[83],"74.3":[85],"dB":[86,91],"within":[89],"0.3":[90],"comparing":[92],"with":[93],"FFT":[95],"counterpart.":[96],"proposed":[98],"achieves":[101],"advantages":[103],"compact":[105],"hardware,":[106],"high":[107],"accuracy,":[108],"flexibility":[111],"adjusting":[113],"stimuli":[115],"are":[117],"important":[118],"features":[119],"for":[120],"applications.":[122]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}