{"id":"https://openalex.org/W2130682515","doi":"https://doi.org/10.1109/ddecs.2008.4538749","title":"An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs","display_name":"An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs","publication_year":2008,"publication_date":"2008-04-01","ids":{"openalex":"https://openalex.org/W2130682515","doi":"https://doi.org/10.1109/ddecs.2008.4538749","mag":"2130682515"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2008.4538749","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2008.4538749","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059823020","display_name":"Stanis\u0142aw Deniziak","orcid":"https://orcid.org/0000-0002-6812-5227"},"institutions":[{"id":"https://openalex.org/I24881138","display_name":"Cracow University of Technology","ror":"https://ror.org/00pdej676","country_code":"PL","type":"education","lineage":["https://openalex.org/I24881138"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Stanislaw Deniziak","raw_affiliation_strings":["Department of Computer Engineering, Cracow University of Technology, Cracow, Poland","Dept. of Comput. Eng., Cracow Univ. of Technol., Cracow"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Cracow University of Technology, Cracow, Poland","institution_ids":["https://openalex.org/I24881138"]},{"raw_affiliation_string":"Dept. of Comput. Eng., Cracow Univ. of Technol., Cracow","institution_ids":["https://openalex.org/I24881138"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039557003","display_name":"M. Wi\u015bniewski","orcid":"https://orcid.org/0000-0001-6795-6216"},"institutions":[{"id":"https://openalex.org/I169109204","display_name":"Kielce University of Technology","ror":"https://ror.org/01zywja13","country_code":"PL","type":"education","lineage":["https://openalex.org/I169109204"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Mariusz Wisniewski","raw_affiliation_strings":["Department of Computer Science, Kielce University of Technology, Kielce, Poland","Dept of Computer Science, Kielce University of Technology, Al. 1000-lecia PP 7, 25-314 Kielce, Poland, e-mail: kinmw@eden.tu.kielce.pl#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Kielce University of Technology, Kielce, Poland","institution_ids":["https://openalex.org/I169109204"]},{"raw_affiliation_string":"Dept of Computer Science, Kielce University of Technology, Al. 1000-lecia PP 7, 25-314 Kielce, Poland, e-mail: kinmw@eden.tu.kielce.pl#TAB#","institution_ids":["https://openalex.org/I169109204"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5059823020"],"corresponding_institution_ids":["https://openalex.org/I24881138"],"apc_list":null,"apc_paid":null,"fwci":0.9988,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.78737133,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":"9","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.8367525339126587},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.8366438150405884},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7774196863174438},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7575826644897461},{"id":"https://openalex.org/keywords/functional-decomposition","display_name":"Functional decomposition","score":0.72817063331604},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7037160992622375},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5293527245521545},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.48314350843429565},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35137540102005005},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34929555654525757},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.33476996421813965},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24196258187294006},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1529647707939148},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14412438869476318},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.0662824809551239}],"concepts":[{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.8367525339126587},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.8366438150405884},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7774196863174438},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7575826644897461},{"id":"https://openalex.org/C12145135","wikidata":"https://www.wikidata.org/wiki/Q5215396","display_name":"Functional decomposition","level":2,"score":0.72817063331604},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7037160992622375},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5293527245521545},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.48314350843429565},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35137540102005005},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34929555654525757},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.33476996421813965},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24196258187294006},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1529647707939148},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14412438869476318},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0662824809551239},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2008.4538749","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2008.4538749","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W142838967","https://openalex.org/W150382073","https://openalex.org/W1544620635","https://openalex.org/W1987847196","https://openalex.org/W2004540799","https://openalex.org/W2109097182","https://openalex.org/W2115731525","https://openalex.org/W2122100106","https://openalex.org/W2122356641","https://openalex.org/W2153886208","https://openalex.org/W2161114343","https://openalex.org/W2163402454","https://openalex.org/W4229640683","https://openalex.org/W6606109571","https://openalex.org/W6632451215"],"related_works":["https://openalex.org/W2155289750","https://openalex.org/W4231267350","https://openalex.org/W2024574431","https://openalex.org/W2117300767","https://openalex.org/W2159724425","https://openalex.org/W2157535420","https://openalex.org/W2374017528","https://openalex.org/W1570722643","https://openalex.org/W4301373716","https://openalex.org/W4285503609"],"abstract_inverted_index":{"In":[0,23],"this":[1,24],"paper":[2],"a":[3],"method":[4,44,60],"for":[5,68],"decomposition":[6,32],"of":[7,20,28,42,65],"functions":[8],"with":[9,18],"multi-valued":[10],"inputs":[11],"is":[12,15,34,45],"presented.":[13],"Decomposition":[14],"performed":[16],"simultaneously":[17],"encoding":[19,30,48],"symbolic":[21],"values.":[22],"way":[25],"an":[26],"impact":[27],"input":[29],"on":[31],"efficiency":[33],"taken":[35],"into":[36],"consideration":[37],"during":[38],"optimization.":[39],"The":[40],"goal":[41],"our":[43],"to":[46],"find":[47],"that":[49,57],"maximally":[50],"simplifies":[51],"functional":[52],"decomposition.":[53],"Experimental":[54],"results":[55],"showed":[56],"the":[58,63],"presented":[59],"significantly":[61],"reduces":[62],"cost":[64],"FPGA":[66],"implementations":[67],"most":[69],"evaluated":[70],"benchmarks.":[71]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}