{"id":"https://openalex.org/W2130471510","doi":"https://doi.org/10.1109/ddecs.2007.4295261","title":"Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA's","display_name":"Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA's","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W2130471510","doi":"https://doi.org/10.1109/ddecs.2007.4295261","mag":"2130471510"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2007.4295261","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2007.4295261","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036301361","display_name":"Grzegorz Borowik","orcid":"https://orcid.org/0000-0003-4148-4817"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Grzegorz Borowik","raw_affiliation_strings":["Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","Warsaw Univ. of Technol., Warsaw"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Warsaw Univ. of Technol., Warsaw","institution_ids":["https://openalex.org/I108403487"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016478346","display_name":"B.J. Falkowski","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Bogdan Falkowski","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","Nanyang Technological University, School of Electrical & Electronic Engineering, 50 Nanyang Avenue, Singapore 639798"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]},{"raw_affiliation_string":"Nanyang Technological University, School of Electrical & Electronic Engineering, 50 Nanyang Avenue, Singapore 639798","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051919904","display_name":"Tadeusz \u0141uba","orcid":"https://orcid.org/0000-0002-4965-7842"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Tadeusz Luba","raw_affiliation_strings":["Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","Warsaw University of Technology, Institute of Telecommunications, Nowowiejska 15/19, 00-665, Warsaw, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Warsaw University of Technology, Institute of Telecommunications, Nowowiejska 15/19, 00-665, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.0281,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.96422846,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"3","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7800321578979492},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7388036251068115},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.5841319561004639},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5447250008583069},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5258976817131042},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5046678781509399},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.47816237807273865},{"id":"https://openalex.org/keywords/graph-coloring","display_name":"Graph coloring","score":0.4440891444683075},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44198206067085266},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.42964833974838257},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.4253450632095337},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3929654657840729},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3279988765716553},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3213921785354614},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2922515869140625},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.20634686946868896},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10820698738098145},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09595388174057007},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08046483993530273}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7800321578979492},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7388036251068115},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.5841319561004639},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5447250008583069},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5258976817131042},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5046678781509399},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.47816237807273865},{"id":"https://openalex.org/C76946457","wikidata":"https://www.wikidata.org/wiki/Q504843","display_name":"Graph coloring","level":3,"score":0.4440891444683075},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44198206067085266},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.42964833974838257},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.4253450632095337},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3929654657840729},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3279988765716553},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3213921785354614},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2922515869140625},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.20634686946868896},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10820698738098145},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09595388174057007},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08046483993530273},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2007.4295261","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2007.4295261","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W142838967","https://openalex.org/W591480010","https://openalex.org/W1487312611","https://openalex.org/W1522506659","https://openalex.org/W1544620635","https://openalex.org/W1975889363","https://openalex.org/W1986557009","https://openalex.org/W2041871970","https://openalex.org/W2059677035","https://openalex.org/W2069533828","https://openalex.org/W2112372316","https://openalex.org/W2125458961","https://openalex.org/W2138973479","https://openalex.org/W2147250303","https://openalex.org/W2317462728","https://openalex.org/W2540380125","https://openalex.org/W2612314725","https://openalex.org/W6617595504","https://openalex.org/W6629219168","https://openalex.org/W6632451215","https://openalex.org/W7008002751"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2316202402","https://openalex.org/W4301373716","https://openalex.org/W1970410908","https://openalex.org/W2782719366","https://openalex.org/W1518382973"],"abstract_inverted_index":{"Modern":[0],"FPLD":[1],"devices":[2],"have":[3],"a":[4,90,93,98,117,119],"very":[5],"complex":[6],"structure.":[7],"They":[8],"combine":[9],"PLA-like":[10],"structures":[11],"as":[12,14,53],"well":[13],"FPGA's":[15,133],"and":[16,77],"even":[17],"memory-based":[18],"structures.":[19],"However,":[20],"the":[21,31,34,57,68,74,81,105],"lack":[22],"of":[23,33,47,56,70,73,92,109,111,125,132],"an":[24,44,51,54],"appropriate":[25],"synthesis":[26],"method":[27,86],"does":[28],"not":[29],"allow":[30],"features":[32],"modern":[35],"FPLD's":[36],"to":[37,80,97],"be":[38],"fully":[39],"exploited.":[40],"In":[41],"this":[42,103],"paper,":[43],"important":[45],"problem":[46,96],"state":[48,82,94],"assignment":[49,95],"for":[50,123],"FSM":[52,62],"extension":[55],"previous":[58],"research":[59],"on":[60,89],"ROM-based":[61],"implementation":[63,124],"is":[64,87,114],"presented.":[65],"We":[66],"pinpoint":[67],"sources":[69],"additional":[71],"optimization":[72],"functional":[75],"decomposition":[76],"relate":[78],"them":[79],"encoding":[83],"conditions.":[84],"The":[85],"based":[88],"reduction":[91],"graph":[99],"coloring":[100],"problem.":[101],"To":[102],"end,":[104],"so":[106],"called":[107],"multi-graph":[108],"incompatibility":[110],"memory":[112,130],"T-words":[113],"applied.":[115],"As":[116],"result,":[118],"new":[120],"design":[121],"technique":[122],"sequential":[126],"circuits":[127],"using":[128],"embedded":[129],"blocks":[131],"has":[134],"been":[135],"developed.":[136],"Preliminary":[137],"experimental":[138],"results":[139],"are":[140],"extremely":[141],"encouraging.":[142]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}