{"id":"https://openalex.org/W2117134894","doi":"https://doi.org/10.1109/ddecs.2006.1649635","title":"Functional-oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage","display_name":"Functional-oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage","publication_year":2006,"publication_date":"2006-07-10","ids":{"openalex":"https://openalex.org/W2117134894","doi":"https://doi.org/10.1109/ddecs.2006.1649635","mag":"2117134894"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2006.1649635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2006.1649635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051341037","display_name":"F. Guerreiro","orcid":"https://orcid.org/0000-0001-6057-3909"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"F. Guerreiro","raw_affiliation_strings":["INESC-ID, Lisboa, Portugal","IST, INESC-ID, Lisboa, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"IST, INESC-ID, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018531470","display_name":"J. Semi\u00e3o","orcid":"https://orcid.org/0000-0002-7667-7910"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J. Semiao","raw_affiliation_strings":["IST, INESC-ID, Lisboa, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IST, INESC-ID, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067035227","display_name":"Aaron Pierce","orcid":"https://orcid.org/0000-0002-6238-7429"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I4210120733","display_name":"Tecmic (Portugal)","ror":"https://ror.org/02jz9yj75","country_code":"PT","type":"company","lineage":["https://openalex.org/I4210120733"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"A. Pierce","raw_affiliation_strings":["IST, INESC-ID, Lisboa, Portugal","TECMIC, Porto Salvo, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IST, INESC-ID, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"TECMIC, Porto Salvo, Portugal","institution_ids":["https://openalex.org/I4210120733"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047445549","display_name":"Marcelino Santos","orcid":"https://orcid.org/0000-0002-2091-1165"},"institutions":[{"id":"https://openalex.org/I4210120733","display_name":"Tecmic (Portugal)","ror":"https://ror.org/02jz9yj75","country_code":"PT","type":"company","lineage":["https://openalex.org/I4210120733"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"M.B. Santos","raw_affiliation_strings":["TECMIC, Porto Salvo, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TECMIC, Porto Salvo, Portugal","institution_ids":["https://openalex.org/I4210120733"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058862498","display_name":"J.P. Teixeira","orcid":"https://orcid.org/0000-0002-0379-6257"},"institutions":[{"id":"https://openalex.org/I71503853","display_name":"University of Algarve","ror":"https://ror.org/014g34x36","country_code":"PT","type":"education","lineage":["https://openalex.org/I71503853"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"I.M. Teixeira","raw_affiliation_strings":["EST, Univ. Algarve, Faro, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"EST, Univ. Algarve, Faro, Portugal","institution_ids":["https://openalex.org/I71503853"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"277","last_page":"282"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.6168039441108704},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6161872744560242},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5899434089660645},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5164468288421631},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.5027954578399658},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5007634162902832},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4842483699321747},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4308106601238251},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3656243681907654},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2945089340209961},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08976024389266968}],"concepts":[{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.6168039441108704},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6161872744560242},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5899434089660645},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5164468288421631},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.5027954578399658},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5007634162902832},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4842483699321747},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4308106601238251},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3656243681907654},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2945089340209961},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08976024389266968},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2006.1649635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2006.1649635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1576082865","https://openalex.org/W1595368737","https://openalex.org/W1905213452","https://openalex.org/W2119691242","https://openalex.org/W2120511739","https://openalex.org/W2137549092","https://openalex.org/W2155976207","https://openalex.org/W2161329778","https://openalex.org/W4232026127","https://openalex.org/W4232703903","https://openalex.org/W4246972245"],"related_works":["https://openalex.org/W2091833418","https://openalex.org/W2913077774","https://openalex.org/W2021253405","https://openalex.org/W2145089576","https://openalex.org/W1986228509","https://openalex.org/W2543176856","https://openalex.org/W2154529098","https://openalex.org/W2109319621","https://openalex.org/W1854778394","https://openalex.org/W2165948443"],"abstract_inverted_index":{"New":[0],"product":[1],"development":[2],"using":[3],"nanometer":[4],"semiconductor":[5],"technologies":[6],"require":[7],"high-quality":[8,60],"BIST":[9,62,70],"solutions":[10,18],"able":[11],"to":[12,56,75,115,133],"uncover":[13,89],"dynamic":[14,46],"faults.":[15,120],"Most":[16],"existing":[17],"rely":[19],"on":[20],"test-per-scan":[21],"BIST,":[22],"for":[23,64],"high":[24,116],"fault":[25,47],"coverage.":[26],"However,":[27],"reconfiguration,":[28],"in":[29,36,85,99,158],"test":[30,86],"mode,":[31],"may":[32],"significantly":[33],"modify":[34],"delays":[35],"signal":[37],"paths,":[38],"thus":[39],"reducing":[40],"the":[41,79,101,135,144,159],"degree":[42],"of":[43,45,52,78,118,147],"confidence":[44],"coverage":[48,117],"values.":[49],"The":[50,68,153],"purpose":[51],"this":[53],"paper":[54],"is":[55,72,93,104,110,138],"present":[57],"a":[58,96,107],"new":[59],"test-per-clock":[61],"methodology":[63,71,154],"sequential":[65,76,102],"digital":[66],"systems.":[67],"proposed":[69],"an":[73,141,148],"extension":[74],"systems":[77],"masked-based":[80],"(or":[81],"m-BIST)":[82],"methodology.":[83],"Determinism":[84],"patterns":[87,113],"(to":[88],"random-pattern":[90],"resistant":[91],"faults)":[92],"inserted":[94],"with":[95,140],"low-intrusion":[97],"scheme,":[98],"which":[100,137],"behavior":[103],"preserved,":[105],"and":[106,125],"bit-flipping":[108],"technique":[109],"used.":[111],"Functional-oriented":[112],"lead":[114],"structural":[119],"Both":[121],"academic":[122],"(VeriDOS,":[123],"ASCOPA)":[124],"commercial":[126],"(Design":[127],"Visiontrade":[128],"Verifaulttrade":[129],"tools":[130],"are":[131],"used":[132],"implement":[134],"methodology,":[136],"demonstrated":[139],"industrial":[142,160],"design,":[143],"PIC":[145],"controller":[146],"electric":[149],"static":[150],"power":[151],"meter.":[152],"has":[155],"been":[156],"incorporated":[157],"partner":[161],"design":[162],"flow":[163]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
