{"id":"https://openalex.org/W2155509389","doi":"https://doi.org/10.1109/ddecs.2006.1649614","title":"Probabilistic Testability Analysis and DFT Methods at RTL","display_name":"Probabilistic Testability Analysis and DFT Methods at RTL","publication_year":2006,"publication_date":"2006-07-10","ids":{"openalex":"https://openalex.org/W2155509389","doi":"https://doi.org/10.1109/ddecs.2006.1649614","mag":"2155509389"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2006.1649614","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2006.1649614","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047648876","display_name":"J. Fernandes","orcid":"https://orcid.org/0000-0002-1663-3334"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J.M. Fernandes","raw_affiliation_strings":["IST/INESC, Lisboa, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IST/INESC, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047445549","display_name":"Marcelino Santos","orcid":"https://orcid.org/0000-0002-2091-1165"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"M.B. Santos","raw_affiliation_strings":["IST/INESC, Lisboa, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IST/INESC, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001327675","display_name":"Arlindo L. Oliveira","orcid":"https://orcid.org/0000-0001-8638-5594"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"A.L. Oliveira","raw_affiliation_strings":["IST/INESC, Lisboa, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IST/INESC, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004981668","display_name":"Jo\u00e3o Teixeira","orcid":"https://orcid.org/0000-0001-9943-3284"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"J.C. Teixeira","raw_affiliation_strings":["IST/INESC, Lisboa, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IST/INESC, Lisboa, Portugal","institution_ids":["https://openalex.org/I121345201"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I121345201"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":null,"first_page":"214","last_page":"215"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.848121166229248},{"id":"https://openalex.org/keywords/observability","display_name":"Observability","score":0.6653566360473633},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6603533029556274},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6210151314735413},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5979241132736206},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.5803053379058838},{"id":"https://openalex.org/keywords/probabilistic-logic","display_name":"Probabilistic logic","score":0.510744571685791},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.48224931955337524},{"id":"https://openalex.org/keywords/controllability","display_name":"Controllability","score":0.4335017800331116},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41236791014671326},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.37079882621765137},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.24184593558311462},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22843962907791138},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.13051071763038635},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11213284730911255},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0996447205543518}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.848121166229248},{"id":"https://openalex.org/C36299963","wikidata":"https://www.wikidata.org/wiki/Q1369844","display_name":"Observability","level":2,"score":0.6653566360473633},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6603533029556274},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6210151314735413},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5979241132736206},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.5803053379058838},{"id":"https://openalex.org/C49937458","wikidata":"https://www.wikidata.org/wiki/Q2599292","display_name":"Probabilistic logic","level":2,"score":0.510744571685791},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.48224931955337524},{"id":"https://openalex.org/C48209547","wikidata":"https://www.wikidata.org/wiki/Q1331104","display_name":"Controllability","level":2,"score":0.4335017800331116},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41236791014671326},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.37079882621765137},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.24184593558311462},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22843962907791138},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.13051071763038635},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11213284730911255},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0996447205543518},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2006.1649614","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2006.1649614","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1972173228","https://openalex.org/W2011848140","https://openalex.org/W2074985862","https://openalex.org/W2083177010","https://openalex.org/W2103258167","https://openalex.org/W2103825248","https://openalex.org/W2120511739","https://openalex.org/W4230203075","https://openalex.org/W4232026127","https://openalex.org/W4232703903"],"related_works":["https://openalex.org/W2332386680","https://openalex.org/W1983142522","https://openalex.org/W1986570998","https://openalex.org/W2782529250","https://openalex.org/W2037921533","https://openalex.org/W2508171592","https://openalex.org/W2801563517","https://openalex.org/W2130864543","https://openalex.org/W2068126039","https://openalex.org/W2041749520"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"probabilistic":[3],"methods":[4,59],"for":[5,44,87,92],"testability":[6,57,107],"analysis":[7,58],"at":[8,47],"RTL":[9,48,69],"and":[10,19,82,94,99,109,117],"their":[11],"use":[12],"to":[13],"guide":[14],"DFT":[15],"techniques":[16],"like":[17],"partial-scan":[18,93],"TPI.":[20],"Controllability":[21],"is":[22,54,97,103],"analyzed":[23],"using":[24,121],"an":[25,38],"approach":[26],"that":[27,65,75],"takes":[28],"into":[29],"account":[30],"correlations":[31],"within":[32],"pre-defined":[33],"groups":[34],"formed":[35],"based":[36,49,104],"on":[37,50,105,110],"originally":[39],"proposed":[40,98,115],"heuristic.":[41],"A":[42,90],"method":[43],"observability":[45],"computation":[46],"the":[51,72,77,80,84,88,106,122],"Boolean":[52],"difference":[53],"presented.":[55],"These":[56],"were":[60],"implemented":[61],"in":[62],"a":[63,67,111],"tool":[64],"reads":[66],"Verilog":[68],"description,":[70],"solves":[71],"Chapman-Kolmogorov":[73],"equations":[74],"describe":[76],"steady-state":[78],"of":[79],"circuit,":[81],"outputs":[83],"computed":[85],"values":[86],"testability.":[89],"methodology":[91,102,118],"TPI":[95],"optimization":[96],"implemented.":[100],"The":[101,114],"metrics":[108],"\"DFT":[112],"dictionary\".":[113],"heuristic":[116],"are":[119],"evaluated":[120],"ITC99":[123],"benchmark":[124],"circuits":[125]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}