{"id":"https://openalex.org/W2109712898","doi":"https://doi.org/10.1109/ddecs.2006.1649597","title":"Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow","display_name":"Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow","publication_year":2006,"publication_date":"2006-07-10","ids":{"openalex":"https://openalex.org/W2109712898","doi":"https://doi.org/10.1109/ddecs.2006.1649597","mag":"2109712898"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2006.1649597","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2006.1649597","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100645455","display_name":"Mohamed Abbas","orcid":"https://orcid.org/0000-0002-3141-2900"},"institutions":[{"id":"https://openalex.org/I114132059","display_name":"Tokyo Electron (Japan)","ror":"https://ror.org/05gd76j39","country_code":"JP","type":"company","lineage":["https://openalex.org/I114132059"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Abbas","raw_affiliation_strings":["Department of Electronic Engineering, University of Tokyo, Japan","Dept of Electron. Eng., Tokyo Univ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Dept of Electron. Eng., Tokyo Univ","institution_ids":["https://openalex.org/I114132059"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I114132059","display_name":"Tokyo Electron (Japan)","ror":"https://ror.org/05gd76j39","country_code":"JP","type":"company","lineage":["https://openalex.org/I114132059"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Ikeda","raw_affiliation_strings":["Tokyo Daigaku, Bunkyo-ku, Tokyo, JP","Dept of Electron. Eng., Tokyo Univ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Daigaku, Bunkyo-ku, Tokyo, JP","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Dept of Electron. Eng., Tokyo Univ","institution_ids":["https://openalex.org/I114132059"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I114132059","display_name":"Tokyo Electron (Japan)","ror":"https://ror.org/05gd76j39","country_code":"JP","type":"company","lineage":["https://openalex.org/I114132059"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Asada","raw_affiliation_strings":["Tokyo Daigaku, Bunkyo-ku, Tokyo, JP","Dept of Electron. Eng., Tokyo Univ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Daigaku, Bunkyo-ku, Tokyo, JP","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Dept of Electron. Eng., Tokyo Univ","institution_ids":["https://openalex.org/I114132059"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15552093,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"145","last_page":"146"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7674503326416016},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6308405995368958},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6095391511917114},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.6060379147529602},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5795546770095825},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.564619243144989},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.520756721496582},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.48980188369750977},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.47692176699638367},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.47020986676216125},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.46062013506889343},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.42565208673477173},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.42460396885871887},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.42361634969711304},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.42078667879104614},{"id":"https://openalex.org/keywords/semiconductor-device-modeling","display_name":"Semiconductor device modeling","score":0.4117380976676941},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3320283889770508},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2822023630142212},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25321197509765625},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11813440918922424},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.07771721482276917}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7674503326416016},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6308405995368958},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6095391511917114},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.6060379147529602},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5795546770095825},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.564619243144989},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.520756721496582},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.48980188369750977},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.47692176699638367},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.47020986676216125},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.46062013506889343},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.42565208673477173},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.42460396885871887},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.42361634969711304},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.42078667879104614},{"id":"https://openalex.org/C4775677","wikidata":"https://www.wikidata.org/wiki/Q7449393","display_name":"Semiconductor device modeling","level":3,"score":0.4117380976676941},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3320283889770508},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2822023630142212},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25321197509765625},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11813440918922424},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.07771721482276917},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2006.1649597","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2006.1649597","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5799999833106995,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1524324089","https://openalex.org/W2099567510","https://openalex.org/W2108640769","https://openalex.org/W2145884136","https://openalex.org/W2150188214","https://openalex.org/W2572573702","https://openalex.org/W6631545134"],"related_works":["https://openalex.org/W2108396794","https://openalex.org/W2178512053","https://openalex.org/W2171566066","https://openalex.org/W1900707063","https://openalex.org/W2099984297","https://openalex.org/W127821896","https://openalex.org/W2114346412","https://openalex.org/W2100280798","https://openalex.org/W1485027372","https://openalex.org/W2123150326"],"abstract_inverted_index":{"In":[0],"this":[1,45],"paper,":[2],"we":[3],"present":[4],"a":[5,15,62],"methodology":[6],"to":[7,54],"evaluate":[8],"the":[9,29,48,50,56,59,70,73,84,90,101],"noise-induced":[10],"logic":[11,21],"error":[12,22],"probability":[13,23],"in":[14,26],"given":[16],"CMOS":[17,115],"digital":[18],"design.":[19,63],"The":[20,64,80,104],"is":[24,52,66],"modeled":[25],"terms":[27],"of":[28,47,95],"operating":[30],"supply":[31],"voltage,":[32,35],"transistor":[33],"threshold":[34],"input":[36],"static":[37],"probabilities,":[38],"circuit":[39],"configuration":[40],"and":[41],"noise":[42,60,78],"level.":[43],"At":[44],"stage":[46],"work,":[49],"model":[51,65,85],"used":[53],"locate":[55],"weak-nodes":[57],"against":[58],"within":[61],"tested":[67],"by":[68,110],"comparing":[69],"results":[71,86,106],"with":[72,89],"transistor-level":[74],"simulation":[75,91,102,105],"at":[76],"specific":[77],"levels.":[79],"comparison":[81],"shows":[82],"that":[83],"fit":[87],"well":[88],"achieving":[92],"speedup":[93],"factor":[94],"more":[96],"than":[97],"1000":[98],"times":[99],"over":[100],"tool.":[103],"have":[107],"been":[108],"obtained":[109],"using":[111],"HSPICE,":[112],"assuming":[113],"0.18mum":[114],"technology":[116]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}