{"id":"https://openalex.org/W2160054859","doi":"https://doi.org/10.1109/ddecs.2006.1649567","title":"Comprehensive design of a high frequency PLL synthesizer for ZigBee application","display_name":"Comprehensive design of a high frequency PLL synthesizer for ZigBee application","publication_year":2006,"publication_date":"2006-07-10","ids":{"openalex":"https://openalex.org/W2160054859","doi":"https://doi.org/10.1109/ddecs.2006.1649567","mag":"2160054859"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2006.1649567","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2006.1649567","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042243069","display_name":"Andr\u00e1s Tim\u00e1r","orcid":null},"institutions":[{"id":"https://openalex.org/I29770179","display_name":"Budapest University of Technology and Economics","ror":"https://ror.org/02w42ss30","country_code":"HU","type":"education","lineage":["https://openalex.org/I29770179"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"A. Timar","raw_affiliation_strings":["Department of Electron Devices, Budapest University of Technology and Economics, Budapest, Hungary"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electron Devices, Budapest University of Technology and Economics, Budapest, Hungary","institution_ids":["https://openalex.org/I29770179"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049326473","display_name":"Abel Vamos","orcid":null},"institutions":[{"id":"https://openalex.org/I29770179","display_name":"Budapest University of Technology and Economics","ror":"https://ror.org/02w42ss30","country_code":"HU","type":"education","lineage":["https://openalex.org/I29770179"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"A. Vamos","raw_affiliation_strings":["Department of Electron Devices, Budapest University of Technology and Economics, Budapest, Hungary"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electron Devices, Budapest University of Technology and Economics, Budapest, Hungary","institution_ids":["https://openalex.org/I29770179"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015047710","display_name":"Gerg\u0151 Bogn\u00e1r","orcid":"https://orcid.org/0000-0001-7818-5760"},"institutions":[{"id":"https://openalex.org/I29770179","display_name":"Budapest University of Technology and Economics","ror":"https://ror.org/02w42ss30","country_code":"HU","type":"education","lineage":["https://openalex.org/I29770179"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"G. Bognar","raw_affiliation_strings":["Department of Electron Devices, Budapest University of Technology and Economics, Budapest, Hungary"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electron Devices, Budapest University of Technology and Economics, Budapest, Hungary","institution_ids":["https://openalex.org/I29770179"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I29770179"],"apc_list":null,"apc_paid":null,"fwci":2.3008,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.88780121,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"3","issue":null,"first_page":"37","last_page":"41"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8249025344848633},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.7590874433517456},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.7140068411827087},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5916527509689331},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5890796184539795},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5871438980102539},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.46187639236450195},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.45964810252189636},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4481993615627289},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.42045900225639343},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.41305628418922424},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.38368237018585205},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2855674624443054},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2824626863002777},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2613826394081116},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25144731998443604},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.08370280265808105}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8249025344848633},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.7590874433517456},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.7140068411827087},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5916527509689331},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5890796184539795},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5871438980102539},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.46187639236450195},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.45964810252189636},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4481993615627289},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.42045900225639343},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.41305628418922424},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.38368237018585205},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2855674624443054},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2824626863002777},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2613826394081116},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25144731998443604},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.08370280265808105}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2006.1649567","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2006.1649567","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W146784561","https://openalex.org/W1567307726","https://openalex.org/W1573278177","https://openalex.org/W1775840686","https://openalex.org/W1982839493","https://openalex.org/W2107241393","https://openalex.org/W2157450557","https://openalex.org/W6605992514"],"related_works":["https://openalex.org/W2050593896","https://openalex.org/W2011064899","https://openalex.org/W1975133264","https://openalex.org/W2081086825","https://openalex.org/W2390006665","https://openalex.org/W2373829667","https://openalex.org/W4281992395","https://openalex.org/W1528236714","https://openalex.org/W2535122132","https://openalex.org/W2160054859"],"abstract_inverted_index":{"Time-to-market":[0],"demands":[1],"shorter":[2],"design":[3,26,33,46,63],"period":[4],"of":[5,35,114,122,162],"applied":[6],"semiconductor":[7],"devices.":[8],"For":[9],"this":[10,29,59,153,156],"reason":[11],"the":[12,15,25,61,71,95,110,115,142,146,158,163],"iteration":[13],"steps,":[14],"simulation":[16,160],"time":[17],"and":[18,43,76],"repetitions":[19],"have":[20,86],"to":[21,87,99,141],"be":[22,88,100,167],"minimized":[23],"along":[24],"flow.":[27],"In":[28,58,155],"paper":[30],"a":[31,36,123],"new":[32],"method":[34],"phase":[37],"locked":[38],"loop":[39],"(PLL)":[40],"frequency":[41,133],"synthesizer":[42,51],"its":[44],"complete":[45,96],"flow":[47],"is":[48,52,134],"introduced.":[49],"This":[50,82],"designed":[53,101,149],"mainly":[54],"for":[55,150],"ZigBee":[56,143],"application.":[57],"case":[60],"top-down":[62],"methodology":[64],"was":[65],"used.":[66],"At":[67],"higher":[68],"hierarchy":[69],"levels":[70],"Verilog-AMS":[72],"hardware":[73],"description":[74],"language":[75],"various":[77],"Matlab":[78],"tools":[79],"were":[80,129,148],"applied.":[81],"analogue":[83],"system":[84,165],"will":[85,166],"realized":[89],"on":[90,109,152],"0.35mum":[91],"CMOS":[92],"technology,":[93],"so":[94],"layout":[97],"has":[98,106],"as":[102,169],"well.":[103],"The":[104,131],"work":[105],"been":[107],"focused":[108],"main":[111],"critical":[112],"element":[113],"PLL":[116],"circuit,":[117],"therefore":[118],"two":[119],"different":[120],"types":[121],"voltage":[124],"controlled":[125],"oscillator":[126],"(VCO)":[127],"blocks":[128],"realized.":[130],"carrier":[132],"around":[135],"2.4":[136],"GHz":[137],"during":[138],"transmission":[139],"according":[140],"standard,":[144],"thus":[145],"VCOs":[147],"operating":[151],"frequency.":[154],"paper,":[157],"mixed-signal":[159],"results":[161],"entire":[164],"introduced,":[168],"well":[170]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
