{"id":"https://openalex.org/W2101722483","doi":"https://doi.org/10.1109/ddecs.2006.1649565","title":"Six subthreshold full adder cells characterized in 90 nm CMOS technology","display_name":"Six subthreshold full adder cells characterized in 90 nm CMOS technology","publication_year":2006,"publication_date":"2006-07-10","ids":{"openalex":"https://openalex.org/W2101722483","doi":"https://doi.org/10.1109/ddecs.2006.1649565","mag":"2101722483"},"language":"en","primary_location":{"id":"doi:10.1109/ddecs.2006.1649565","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2006.1649565","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109914049","display_name":"K. Granhaug","orcid":null},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":true,"raw_author_name":"K. Granhaug","raw_affiliation_strings":["Department of Informatics, University of Oslo, Oslo, Norway","Dept. of Informatics, Oslo Univ"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, University of Oslo, Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]},{"raw_affiliation_string":"Dept. of Informatics, Oslo Univ","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026627174","display_name":"Snorre Aunet","orcid":"https://orcid.org/0000-0002-6465-8886"},"institutions":[{"id":"https://openalex.org/I184942183","display_name":"University of Oslo","ror":"https://ror.org/01xtthb56","country_code":"NO","type":"education","lineage":["https://openalex.org/I184942183"]}],"countries":["NO"],"is_corresponding":false,"raw_author_name":"S. Aunet","raw_affiliation_strings":["Department of Informatics, University of Oslo, Oslo, Norway","Department of Informatics University of Oslo, Oslo, Norway"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, University of Oslo, Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]},{"raw_affiliation_string":"Department of Informatics University of Oslo, Oslo, Norway","institution_ids":["https://openalex.org/I184942183"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5109914049"],"corresponding_institution_ids":["https://openalex.org/I184942183"],"apc_list":null,"apc_paid":null,"fwci":3.0087,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.91021656,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"25","last_page":"30"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.945322573184967},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8391303420066833},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.7803553342819214},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.7766027450561523},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4869195222854614},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4801192283630371},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47821828722953796},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4771565794944763},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4692915380001068},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.46892765164375305},{"id":"https://openalex.org/keywords/product","display_name":"Product (mathematics)","score":0.45940202474594116},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.44002366065979004},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3452553153038025},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3067916929721832},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.24152415990829468},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.23408949375152588},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17101523280143738},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15348675847053528},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1417040228843689}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.945322573184967},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8391303420066833},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.7803553342819214},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.7766027450561523},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4869195222854614},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4801192283630371},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47821828722953796},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4771565794944763},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4692915380001068},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.46892765164375305},{"id":"https://openalex.org/C90673727","wikidata":"https://www.wikidata.org/wiki/Q901718","display_name":"Product (mathematics)","level":2,"score":0.45940202474594116},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.44002366065979004},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3452553153038025},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3067916929721832},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.24152415990829468},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.23408949375152588},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17101523280143738},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15348675847053528},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1417040228843689},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ddecs.2006.1649565","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ddecs.2006.1649565","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8899999856948853,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1539883310","https://openalex.org/W1841730948","https://openalex.org/W1903589471","https://openalex.org/W1955695519","https://openalex.org/W2079826846","https://openalex.org/W2108312065","https://openalex.org/W2108519747","https://openalex.org/W2113192550","https://openalex.org/W2127893664","https://openalex.org/W2138968074","https://openalex.org/W2156121469","https://openalex.org/W2159448561","https://openalex.org/W2168517613","https://openalex.org/W2169872183","https://openalex.org/W6683022472"],"related_works":["https://openalex.org/W2527731084","https://openalex.org/W2619307913","https://openalex.org/W4200113551","https://openalex.org/W2376573441","https://openalex.org/W2187717486","https://openalex.org/W3161678484","https://openalex.org/W4225985484","https://openalex.org/W1863387014","https://openalex.org/W4385009842","https://openalex.org/W3037574826"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,44],"performance":[4],"analysis":[5],"and":[6,37,49,56],"evaluation":[7],"of":[8,59,87],"six":[9],"different":[10],"1-bit":[11],"full":[12,52],"adder":[13],"topologies":[14],"in":[15],"deep":[16],"subthreshold":[17],"operation.":[18],"The":[19],"cells":[20,68],"are":[21,54,64],"characterized":[22],"with":[23],"respect":[24],"to":[25],"delay,":[26],"power":[27,47,89],"consumption,":[28],"driving":[29],"capability,":[30],"power-delay":[31],"product":[32,35],"(PDP),":[33],"energy-delay":[34],"(EDP)":[36],"maximum":[38],"operating":[39,69],"frequency.":[40],"Both":[41],"traditional":[42],"CMOS,":[43],"specialized":[45],"low":[46],"cell":[48],"minority-3":[50],"based":[51],"adders":[53],"simulated":[55],"characterized.":[57],"PDPs":[58],"less":[60,83],"than":[61,84],"200":[62],"aJ":[63],"reported,":[65],"for":[66,75],"FA":[67],"at":[70],"frequencies":[71],"around":[72],"2":[73],"MHz,":[74],"V":[76],"<sub":[77],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[78],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">dd</sub>":[79],"=200":[80],"mV,":[81],"dissipating":[82],"100":[85],"nW":[86],"average":[88]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
