{"id":"https://openalex.org/W4417249643","doi":"https://doi.org/10.1109/dcis67520.2025.11281933","title":"Hardware-Efficient Gaussian and Sobel Filters for Real-Time Image Processing on FPGA","display_name":"Hardware-Efficient Gaussian and Sobel Filters for Real-Time Image Processing on FPGA","publication_year":2025,"publication_date":"2025-11-26","ids":{"openalex":"https://openalex.org/W4417249643","doi":"https://doi.org/10.1109/dcis67520.2025.11281933"},"language":null,"primary_location":{"id":"doi:10.1109/dcis67520.2025.11281933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis67520.2025.11281933","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 40th Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114971655","display_name":"Francisco Albertuz","orcid":"https://orcid.org/0009-0007-0219-7299"},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Francisco Albertuz","raw_affiliation_strings":["Universidad Politécnica de Madrid,Department of Electronic Engineering,Madrid,Spain"],"affiliations":[{"raw_affiliation_string":"Universidad Politécnica de Madrid,Department of Electronic Engineering,Madrid,Spain","institution_ids":["https://openalex.org/I88060688"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059222971","display_name":"Mario Garrido","orcid":"https://orcid.org/0000-0001-5739-3544"},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Mario Garrido","raw_affiliation_strings":["Universidad Politécnica de Madrid,Department of Electronic Engineering,Madrid,Spain"],"affiliations":[{"raw_affiliation_string":"Universidad Politécnica de Madrid,Department of Electronic Engineering,Madrid,Spain","institution_ids":["https://openalex.org/I88060688"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5114971655"],"corresponding_institution_ids":["https://openalex.org/I88060688"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.43420794,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"199","last_page":"204"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10688","display_name":"Image and Signal Denoising Methods","score":0.16300000250339508,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10688","display_name":"Image and Signal Denoising Methods","score":0.16300000250339508,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.13279999792575836,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11019","display_name":"Image Enhancement Techniques","score":0.11069999635219574,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sobel-operator","display_name":"Sobel operator","score":0.8274999856948853},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5659999847412109},{"id":"https://openalex.org/keywords/convolution","display_name":"Convolution (computer science)","score":0.5278000235557556},{"id":"https://openalex.org/keywords/gaussian-filter","display_name":"Gaussian filter","score":0.46299999952316284},{"id":"https://openalex.org/keywords/smoothing","display_name":"Smoothing","score":0.46299999952316284},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.41440001130104065},{"id":"https://openalex.org/keywords/edge-detection","display_name":"Edge detection","score":0.40959998965263367},{"id":"https://openalex.org/keywords/gaussian-blur","display_name":"Gaussian blur","score":0.4074999988079071},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.40369999408721924},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.39340001344680786}],"concepts":[{"id":"https://openalex.org/C30703548","wikidata":"https://www.wikidata.org/wiki/Q1757673","display_name":"Sobel operator","level":5,"score":0.8274999856948853},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7657999992370605},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5659999847412109},{"id":"https://openalex.org/C45347329","wikidata":"https://www.wikidata.org/wiki/Q5166604","display_name":"Convolution (computer science)","level":3,"score":0.5278000235557556},{"id":"https://openalex.org/C3770464","wikidata":"https://www.wikidata.org/wiki/Q775963","display_name":"Smoothing","level":2,"score":0.46299999952316284},{"id":"https://openalex.org/C65892221","wikidata":"https://www.wikidata.org/wiki/Q1113935","display_name":"Gaussian filter","level":3,"score":0.46299999952316284},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4214000105857849},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.41440001130104065},{"id":"https://openalex.org/C193536780","wikidata":"https://www.wikidata.org/wiki/Q1513153","display_name":"Edge detection","level":4,"score":0.40959998965263367},{"id":"https://openalex.org/C104317376","wikidata":"https://www.wikidata.org/wiki/Q1894545","display_name":"Gaussian blur","level":5,"score":0.4074999988079071},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.40369999408721924},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.39340001344680786},{"id":"https://openalex.org/C163716315","wikidata":"https://www.wikidata.org/wiki/Q901177","display_name":"Gaussian","level":2,"score":0.37599998712539673},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.362199991941452},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.34200000762939453},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3418000042438507},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.33250001072883606},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.32249999046325684},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3098999857902527},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3077000081539154},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3043999969959259},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.30219998955726624},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.29989999532699585},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.2992999851703644},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.2953999936580658},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.29179999232292175},{"id":"https://openalex.org/C157899210","wikidata":"https://www.wikidata.org/wiki/Q1395022","display_name":"Convolutional code","level":3,"score":0.28519999980926514},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.28439998626708984},{"id":"https://openalex.org/C2778484313","wikidata":"https://www.wikidata.org/wiki/Q1172540","display_name":"Data stream","level":2,"score":0.27900001406669617},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.27880001068115234},{"id":"https://openalex.org/C55352655","wikidata":"https://www.wikidata.org/wiki/Q304247","display_name":"Median filter","level":4,"score":0.2741999924182892},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.27160000801086426},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.27090001106262207},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.259799987077713},{"id":"https://openalex.org/C104317675","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Digital image processing","level":4,"score":0.2581000030040741},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.25619998574256897}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dcis67520.2025.11281933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis67520.2025.11281933","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 40th Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1604924365","https://openalex.org/W2017745767","https://openalex.org/W2033284816","https://openalex.org/W2069585984","https://openalex.org/W2094505759","https://openalex.org/W2096891952","https://openalex.org/W2155422878","https://openalex.org/W2543897149","https://openalex.org/W2611445287","https://openalex.org/W2680817039","https://openalex.org/W2808739938","https://openalex.org/W2909120052","https://openalex.org/W3163814125","https://openalex.org/W4206724140","https://openalex.org/W4313887421","https://openalex.org/W4401073506","https://openalex.org/W4401607541","https://openalex.org/W4404954017","https://openalex.org/W4407467228","https://openalex.org/W4407475053"],"related_works":[],"abstract_inverted_index":{"This":[0],"work":[1,80],"presents":[2],"compact":[3],"Gaussian":[4],"and":[5,13,35,54,62,101,123,127],"Sobel":[6],"convolutional":[7,136],"filters":[8,34],"for":[9,71],"efficient":[10,38],"image":[11],"smoothing":[12],"edge":[14],"detection":[15],"on":[16],"field-programmable":[17],"gate":[18],"arrays":[19],"(FPGAs).":[20],"To":[21],"design":[22],"the":[23,28,112,116],"architectures,":[24],"we":[25],"mathematically":[26],"analyze":[27],"convolution":[29],"operations":[30],"performed":[31],"by":[32],"both":[33],"develop":[36],"computationally":[37],"implementations.":[39],"We":[40],"also":[41,69,131],"apply":[42],"several":[43,107],"digital":[44],"circuit":[45],"optimization":[46],"techniques,":[47],"such":[48],"as":[49],"resource":[50,98],"sharing,":[51],"operation":[52],"sequencing,":[53],"memory":[55],"optimization,":[56],"to":[57,79,134],"further":[58],"reduce":[59,120],"area":[60],"usage":[61,122,126],"power":[63,102,128],"consumption.":[64,103],"The":[65,91],"proposed":[66,117],"approaches":[67],"are":[68,77,130],"suitable":[70],"real-time":[72],"high-speed":[73],"applications,":[74],"since":[75],"they":[76],"designed":[78],"with":[81,106],"a":[82,87],"continuous":[83],"data":[84],"stream":[85],"at":[86],"high":[88],"clock":[89],"frequency.":[90],"implemented":[92],"circuits":[93],"have":[94],"been":[95],"analyzed":[96],"regarding":[97],"usage,":[99],"speed,":[100],"A":[104],"comparison":[105],"previous":[108],"FPGA":[109],"implementations":[110],"from":[111],"literature":[113],"shows":[114],"that":[115],"designs":[118],"significantly":[119],"logic":[121],"latency.":[124],"Memory":[125],"consumption":[129],"reduced":[132],"compared":[133],"generic":[135],"architectures.":[137]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-12-11T00:00:00"}