{"id":"https://openalex.org/W4417249089","doi":"https://doi.org/10.1109/dcis67520.2025.11281931","title":"Comparative Analysis of Full Adders Based on DTMOS Schmitt-Trigger Standard Cells Operating at Sub-100 mV Supply Voltage","display_name":"Comparative Analysis of Full Adders Based on DTMOS Schmitt-Trigger Standard Cells Operating at Sub-100 mV Supply Voltage","publication_year":2025,"publication_date":"2025-11-26","ids":{"openalex":"https://openalex.org/W4417249089","doi":"https://doi.org/10.1109/dcis67520.2025.11281931"},"language":null,"primary_location":{"id":"doi:10.1109/dcis67520.2025.11281931","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis67520.2025.11281931","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 40th Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Muhammad Umer Khalid","orcid":null},"institutions":[{"id":"https://openalex.org/I204778367","display_name":"Norwegian University of Science and Technology","ror":"https://ror.org/05xg72x27","country_code":"NO","type":"education","lineage":["https://openalex.org/I204778367"]}],"countries":["NO"],"is_corresponding":true,"raw_author_name":"Muhammad Umer Khalid","raw_affiliation_strings":["Norwegian University of Science and Technology (NTNU),Faculty of Information Technology and Electrical Engineering,Department of Electronic Systems,Trondheim,Norway"],"affiliations":[{"raw_affiliation_string":"Norwegian University of Science and Technology (NTNU),Faculty of Information Technology and Electrical Engineering,Department of Electronic Systems,Trondheim,Norway","institution_ids":["https://openalex.org/I204778367"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055804223","display_name":"Trond Ytterdal","orcid":"https://orcid.org/0000-0002-2109-833X"},"institutions":[{"id":"https://openalex.org/I204778367","display_name":"Norwegian University of Science and Technology","ror":"https://ror.org/05xg72x27","country_code":"NO","type":"education","lineage":["https://openalex.org/I204778367"]}],"countries":["NO"],"is_corresponding":false,"raw_author_name":"Trond Ytterdal","raw_affiliation_strings":["Norwegian University of Science and Technology (NTNU),Faculty of Information Technology and Electrical Engineering,Department of Electronic Systems,Trondheim,Norway"],"affiliations":[{"raw_affiliation_string":"Norwegian University of Science and Technology (NTNU),Faculty of Information Technology and Electrical Engineering,Department of Electronic Systems,Trondheim,Norway","institution_ids":["https://openalex.org/I204778367"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026627174","display_name":"Snorre Aunet","orcid":"https://orcid.org/0000-0002-6465-8886"},"institutions":[{"id":"https://openalex.org/I204778367","display_name":"Norwegian University of Science and Technology","ror":"https://ror.org/05xg72x27","country_code":"NO","type":"education","lineage":["https://openalex.org/I204778367"]}],"countries":["NO"],"is_corresponding":false,"raw_author_name":"Snorre Aunet","raw_affiliation_strings":["Norwegian University of Science and Technology (NTNU),Faculty of Information Technology and Electrical Engineering,Department of Electronic Systems,Trondheim,Norway"],"affiliations":[{"raw_affiliation_string":"Norwegian University of Science and Technology (NTNU),Faculty of Information Technology and Electrical Engineering,Department of Electronic Systems,Trondheim,Norway","institution_ids":["https://openalex.org/I204778367"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I204778367"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.3784651,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"182","last_page":"187"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9571999907493591,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9571999907493591,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.012400000356137753,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.0066999997943639755,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.734499990940094},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.7264999747276306},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7150999903678894},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.6133000254631042},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.5623999834060669},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.5092999935150146},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4260999858379364},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4099000096321106},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.40049999952316284}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.734499990940094},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.7264999747276306},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7150999903678894},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.6133000254631042},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.5623999834060669},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.5092999935150146},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49300000071525574},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.46720001101493835},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4260999858379364},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4099000096321106},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.40049999952316284},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.39629998803138733},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.38690000772476196},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.36550000309944153},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33970001339912415},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.33399999141693115},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.32829999923706055},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.31040000915527344},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.30149999260902405},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.2978000044822693},{"id":"https://openalex.org/C128624480","wikidata":"https://www.wikidata.org/wiki/Q1504817","display_name":"Low voltage","level":3,"score":0.2930000126361847},{"id":"https://openalex.org/C22762622","wikidata":"https://www.wikidata.org/wiki/Q628904","display_name":"Operating point","level":2,"score":0.28679999709129333},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.2815999984741211},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.26899999380111694},{"id":"https://openalex.org/C130277099","wikidata":"https://www.wikidata.org/wiki/Q3676605","display_name":"Figure of merit","level":2,"score":0.2549999952316284},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.25450000166893005},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.2533000111579895},{"id":"https://openalex.org/C2987804222","wikidata":"https://www.wikidata.org/wiki/Q5376582","display_name":"End point","level":2,"score":0.2524000108242035}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dcis67520.2025.11281931","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis67520.2025.11281931","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 40th Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1964930576","https://openalex.org/W2083087340","https://openalex.org/W2119935308","https://openalex.org/W2138968074","https://openalex.org/W2157321309","https://openalex.org/W2547708291","https://openalex.org/W2659585261","https://openalex.org/W2800710142","https://openalex.org/W3090292362","https://openalex.org/W3147809611","https://openalex.org/W4285821856","https://openalex.org/W4415378040","https://openalex.org/W4417249456"],"related_works":[],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"a":[3,70,96,99],"comparative":[4],"study":[5],"of":[6,121],"the":[7,77,81,105,122],"Full":[8],"Adders":[9],"(FAs)":[10],"implemented":[11],"using":[12],"DTMOS":[13],"Schmitt-Trigger":[14,100],"(DST)":[15],"standard":[16],"cells":[17],"in":[18],"130":[19],"nm":[20],"SOI":[21],"CMOS":[22],"technology,":[23],"targeting":[24],"ultra-low":[25],"supply":[26],"voltages":[27],"below":[28],"100":[29],"mV.":[30],"Multiple":[31],"DST-based":[32,123],"FA":[33,79,102,108,124],"topologies":[34],"were":[35,67],"designed":[36],"and":[37,51,55,64,88,112],"evaluated":[38],"through":[39],"extensive":[40],"post-layout":[41],"Monte":[42],"Carlo":[43],"simulations":[44],"to":[45,137],"assess":[46],"robustness":[47,111],"under":[48],"process,":[49],"voltage,":[50],"temperature":[52],"(PVT)":[53],"variations":[54],"device":[56],"mismatch.":[57],"Performance":[58],"metrics,":[59],"including":[60],"energy,":[61],"delay,":[62,85],"power,":[63],"energy-delay":[65],"product,":[66],"analyzed":[68],"across":[69],"voltage":[71],"range.":[72],"The":[73,116],"results":[74],"indicate":[75],"that":[76,104],"NAND-only":[78,101,107],"achieves":[80],"highest":[82],"yield,":[83],"lowest":[84],"smallest":[86],"area,":[87],"superior":[89],"energy":[90,114,118],"efficiency":[91],"among":[92],"DST":[93,106],"designs.":[94],"Furthermore,":[95],"comparison":[97],"with":[98],"shows":[103],"offers":[109],"greater":[110],"improved":[113],"efficiency.":[115],"minimum":[117],"point":[119],"(MEP)":[120],"ring":[125],"oscillator":[126],"is":[127],"<tex":[128,138],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[129,139],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$\\mathbf{1":[130,140],"4":[131],"0":[132,142],"~":[133,143],"m":[134,144],"V}$</tex>,":[135],"compared":[136],"7":[141],"V}$</tex>":[145],"for":[146],"its":[147],"ST":[148],"counterpart.":[149]},"counts_by_year":[],"updated_date":"2026-04-23T09:07:50.710637","created_date":"2025-12-11T00:00:00"}