{"id":"https://openalex.org/W4417249345","doi":"https://doi.org/10.1109/dcis67520.2025.11281929","title":"Low Entropy Masking Protection Scheme for Ascon Cipher to Counteract Side-Channel Attacks","display_name":"Low Entropy Masking Protection Scheme for Ascon Cipher to Counteract Side-Channel Attacks","publication_year":2025,"publication_date":"2025-11-26","ids":{"openalex":"https://openalex.org/W4417249345","doi":"https://doi.org/10.1109/dcis67520.2025.11281929"},"language":null,"primary_location":{"id":"doi:10.1109/dcis67520.2025.11281929","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis67520.2025.11281929","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 40th Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043725292","display_name":"Erica Tena\u2010S\u00e1nchez","orcid":"https://orcid.org/0000-0002-8905-5715"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"E. Tena-S\u00e1nchez","raw_affiliation_strings":["Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / University of Seville)"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / University of Seville)","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014057357","display_name":"F. E. Potestad-Ord\u00f3\u0144ez","orcid":"https://orcid.org/0000-0003-4107-2396"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"F. E. Potestad-Ord\u00f3\u00f1ez","raw_affiliation_strings":["Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / University of Seville)"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / University of Seville)","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114972247","display_name":"Miguel Mart\u00edn\u2010Gonz\u00e1lez","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"M. Mart\u00edn-Gonz\u00e1lez","raw_affiliation_strings":["Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / University of Seville)"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / University of Seville)","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5094043715","display_name":"A. Casado-Gal\u00e1n","orcid":"https://orcid.org/0009-0003-1633-243X"},"institutions":[{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"A. Casado-Gal\u00e1n","raw_affiliation_strings":["Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / University of Seville)"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / University of Seville)","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073626271","display_name":"Antonio J. Acosta","orcid":"https://orcid.org/0000-0002-7934-9162"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]},{"id":"https://openalex.org/I4210104545","display_name":"Instituto de Microelectr\u00f3nica de Sevilla","ror":"https://ror.org/01mqtzm43","country_code":"ES","type":"facility","lineage":["https://openalex.org/I134820265","https://openalex.org/I4210104545","https://openalex.org/I4210147934","https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"A. J. Acosta","raw_affiliation_strings":["Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / University of Seville)"],"affiliations":[{"raw_affiliation_string":"Instituto de Microelectrónica de Sevilla IMSE-CNM (CSIC / University of Seville)","institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5043725292"],"corresponding_institution_ids":["https://openalex.org/I4210104545","https://openalex.org/I79238269"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.22072082,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"43","last_page":"48"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.0010999999940395355,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.0007999999797903001,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cipher","display_name":"Cipher","score":0.7067000269889832},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.598800003528595},{"id":"https://openalex.org/keywords/nist","display_name":"NIST","score":0.5852000117301941},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5809999704360962},{"id":"https://openalex.org/keywords/block-cipher","display_name":"Block cipher","score":0.544700026512146},{"id":"https://openalex.org/keywords/running-key-cipher","display_name":"Running key cipher","score":0.4846000075340271},{"id":"https://openalex.org/keywords/block-cipher-mode-of-operation","display_name":"Block cipher mode of operation","score":0.476500004529953}],"concepts":[{"id":"https://openalex.org/C2780221543","wikidata":"https://www.wikidata.org/wiki/Q4681865","display_name":"Cipher","level":3,"score":0.7067000269889832},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.667900025844574},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.598800003528595},{"id":"https://openalex.org/C111219384","wikidata":"https://www.wikidata.org/wiki/Q6954384","display_name":"NIST","level":2,"score":0.5852000117301941},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5809999704360962},{"id":"https://openalex.org/C106544461","wikidata":"https://www.wikidata.org/wiki/Q543151","display_name":"Block cipher","level":3,"score":0.544700026512146},{"id":"https://openalex.org/C64119674","wikidata":"https://www.wikidata.org/wiki/Q7380031","display_name":"Running key cipher","level":4,"score":0.4846000075340271},{"id":"https://openalex.org/C60448319","wikidata":"https://www.wikidata.org/wiki/Q154021","display_name":"Block cipher mode of operation","level":2,"score":0.476500004529953},{"id":"https://openalex.org/C106301342","wikidata":"https://www.wikidata.org/wiki/Q4117933","display_name":"Entropy (arrow of time)","level":2,"score":0.40639999508857727},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.396699994802475},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.36309999227523804},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3626999855041504},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.3598000109195709},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.34040001034736633},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3368000090122223},{"id":"https://openalex.org/C2777402240","wikidata":"https://www.wikidata.org/wiki/Q6783436","display_name":"Masking (illustration)","level":2,"score":0.3098999857902527},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3091000020503998},{"id":"https://openalex.org/C181149355","wikidata":"https://www.wikidata.org/wiki/Q897511","display_name":"Cryptanalysis","level":3,"score":0.3012000024318695},{"id":"https://openalex.org/C28420585","wikidata":"https://www.wikidata.org/wiki/Q2665075","display_name":"Timing attack","level":4,"score":0.2847999930381775},{"id":"https://openalex.org/C38369872","wikidata":"https://www.wikidata.org/wiki/Q7445009","display_name":"Security analysis","level":2,"score":0.2669000029563904}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dcis67520.2025.11281929","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis67520.2025.11281929","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 40th Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1613874182","https://openalex.org/W2154909745","https://openalex.org/W2158457572","https://openalex.org/W2548820325","https://openalex.org/W2622687895","https://openalex.org/W2807866490","https://openalex.org/W2921871778","https://openalex.org/W2950471701","https://openalex.org/W3002366890","https://openalex.org/W3107214918","https://openalex.org/W4360596698","https://openalex.org/W4386328322","https://openalex.org/W4399930929","https://openalex.org/W4404955698","https://openalex.org/W4410741829"],"related_works":[],"abstract_inverted_index":{"Since":[0],"NIST":[1],"selected":[2],"the":[3,10,20,32,51,55,71,92,101,104,125,148,164],"Ascon":[4,56,130],"cipher":[5,12,21],"as":[6],"a":[7,24,78,82,136,151],"finalist":[8],"in":[9,17,50,70,88,110,135],"lightweight":[11],"competition":[13],"for":[14,81],"constrained":[15],"environments":[16],"February":[18],"2023,":[19],"has":[22,107,132,153],"been":[23,68,108,133,154],"focus":[25],"of":[26],"researchers,":[27],"industry":[28],"and":[29,156],"government.":[30],"On":[31],"other":[33],"hand,":[34],"hardware-implemented":[35],"cryptographic":[36],"algorithms":[37],"have":[38,67],"had":[39],"to":[40,90,124,158],"deal":[41],"with":[42,122],"so-called":[43],"Side-Channel":[44],"Attacks":[45],"(SCA)":[46],"since":[47],"their":[48],"emergence":[49],"late":[52],"1990s.":[53],"Although":[54],"algorithm":[57,131],"is":[58,120],"relatively":[59],"recent,":[60],"SCA":[61,145],"attacks":[62,146],"that":[63],"breach":[64],"its":[65],"security":[66,95],"proposed":[69,102],"literature.":[72],"In":[73],"this":[74],"paper,":[75],"we":[76],"present":[77],"design":[79,117],"methodology":[80],"low":[83],"entropy":[84],"masking":[85],"protection":[86],"scheme":[87],"order":[89],"raise":[91],"AscON":[93],"algorithm's":[94],"levels":[96],"against":[97],"SCA.":[98],"To":[99,142],"evaluate":[100],"methodology,":[103],"Ascon's":[105],"permutation":[106],"implemented":[109,116],"an":[111],"Artix-7":[112],"Xilinx":[113],"FPGA.":[114],"The":[115],"area":[118],"overhead":[119],"5.45%":[121],"respect":[123],"unprotected":[126],"implementation.":[127],"A":[128],"complete":[129],"manufactured":[134,157],"65":[137],"nm":[138],"TSMC":[139],"ASIC":[140,165],"technology.":[141],"perform":[143,160],"experimental":[144],"on":[147,163],"ASCON":[149],"ASIC,":[150],"PCB":[152],"designed":[155],"specifically":[159],"power":[161],"measurements":[162],"core.":[166]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-12-11T00:00:00"}