{"id":"https://openalex.org/W4417249454","doi":"https://doi.org/10.1109/dcis67520.2025.11281911","title":"A Programmable, Negative, and Dynamically Biased Sampler for Ultra-Low Power Body-Bias Generators in 18nm FD-SOI","display_name":"A Programmable, Negative, and Dynamically Biased Sampler for Ultra-Low Power Body-Bias Generators in 18nm FD-SOI","publication_year":2025,"publication_date":"2025-11-26","ids":{"openalex":"https://openalex.org/W4417249454","doi":"https://doi.org/10.1109/dcis67520.2025.11281911"},"language":null,"primary_location":{"id":"doi:10.1109/dcis67520.2025.11281911","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis67520.2025.11281911","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 40th Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048896427","display_name":"Till Bergmann","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Tom Bergmann","raw_affiliation_strings":["STMicroelectronics,Crolles,France"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics,Crolles,France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055572985","display_name":"Jo\u00ebl Damiens","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Joel Damiens","raw_affiliation_strings":["STMicroelectronics,Crolles,France"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics,Crolles,France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066990447","display_name":"A. Rueda","orcid":"https://orcid.org/0000-0003-4564-9359"},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Alfonso Hildebrand Rueda","raw_affiliation_strings":["STMicroelectronics,Crolles,France"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics,Crolles,France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006563252","display_name":"Shelby Lacouture","orcid":"https://orcid.org/0000-0002-9449-8844"},"institutions":[{"id":"https://openalex.org/I4210104693","display_name":"STMicroelectronics (France)","ror":"https://ror.org/01c74sd89","country_code":"FR","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210104693"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Stephane Lacouture","raw_affiliation_strings":["STMicroelectronics,Crolles,France"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics,Crolles,France","institution_ids":["https://openalex.org/I4210104693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113859236","display_name":"R\u00e9my Cellier","orcid":null},"institutions":[{"id":"https://openalex.org/I2800958632","display_name":"Institut des Nanotechnologies de Lyon","ror":"https://ror.org/04jsk0b74","country_code":"FR","type":"facility","lineage":["https://openalex.org/I100532134","https://openalex.org/I112936343","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I2800958632","https://openalex.org/I4210095849","https://openalex.org/I48430043","https://openalex.org/I59692284"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Remy Cellier","raw_affiliation_strings":["Institut des Nanotechnologies de Lyon,Villeurbanne,France"],"affiliations":[{"raw_affiliation_string":"Institut des Nanotechnologies de Lyon,Villeurbanne,France","institution_ids":["https://openalex.org/I2800958632"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034203803","display_name":"Nacer Abouchi","orcid":null},"institutions":[{"id":"https://openalex.org/I2800958632","display_name":"Institut des Nanotechnologies de Lyon","ror":"https://ror.org/04jsk0b74","country_code":"FR","type":"facility","lineage":["https://openalex.org/I100532134","https://openalex.org/I112936343","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I2800958632","https://openalex.org/I4210095849","https://openalex.org/I48430043","https://openalex.org/I59692284"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Nacer Abouchi","raw_affiliation_strings":["Institut des Nanotechnologies de Lyon,Villeurbanne,France"],"affiliations":[{"raw_affiliation_string":"Institut des Nanotechnologies de Lyon,Villeurbanne,France","institution_ids":["https://openalex.org/I2800958632"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5048896427"],"corresponding_institution_ids":["https://openalex.org/I4210104693"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.4277931,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"268","last_page":"273"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.8098000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.8098000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.14569999277591705,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.010700000450015068,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5874000191688538},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5703999996185303},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5285000205039978},{"id":"https://openalex.org/keywords/capacitive-sensing","display_name":"Capacitive sensing","score":0.5091000199317932},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4957999885082245},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.47690001130104065},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.47380000352859497},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.4677000045776367},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.45350000262260437}],"concepts":[{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6060000061988831},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5874000191688538},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5703999996185303},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5473999977111816},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5285000205039978},{"id":"https://openalex.org/C206755178","wikidata":"https://www.wikidata.org/wiki/Q1131271","display_name":"Capacitive sensing","level":2,"score":0.5091000199317932},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4957999885082245},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.47690001130104065},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.47380000352859497},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.4677000045776367},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.46140000224113464},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.45350000262260437},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4081000089645386},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.40639999508857727},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3953999876976013},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.37869998812675476},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.36970001459121704},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.36169999837875366},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.3521000146865845},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.34880000352859497},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.2892000079154968},{"id":"https://openalex.org/C2778774385","wikidata":"https://www.wikidata.org/wiki/Q4437810","display_name":"Power management","level":3,"score":0.28299999237060547},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.2809999883174896},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.2800999879837036},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2786000072956085},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.2700999975204468},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2632000148296356},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.259799987077713}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dcis67520.2025.11281911","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis67520.2025.11281911","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 40th Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2021433466","https://openalex.org/W2059834457","https://openalex.org/W2084465580","https://openalex.org/W2111186324","https://openalex.org/W2140322178","https://openalex.org/W2524282698","https://openalex.org/W2920862789"],"related_works":[],"abstract_inverted_index":{"With":[0],"the":[1,9,54,135,177],"rapid":[2],"growth":[3],"of":[4,6,103,134],"Internet":[5],"Things":[7],"(IoT),":[8],"demand":[10],"for":[11,67,131],"Ultra-Low":[12],"Power":[13],"(ULP)":[14],"circuits":[15,20],"increased,":[16],"making":[17,126],"power":[18,94,124,143],"management":[19],"a":[21,61,104,116,128,142,155,166],"critical":[22],"need.":[23],"In":[24],"this":[25,59],"context,":[26],"Fully":[27],"Depleted":[28],"Silicon":[29],"on":[30,172],"Insulator":[31],"(FD-SOI)":[32],"technology":[33,74],"is":[34,48,75,101],"indicated":[35],"thanks":[36],"to":[37,84,92,110,146,165],"an":[38],"enhanced":[39],"body":[40],"biasing":[41],"possibility's.":[42],"An":[43],"Adaptive":[44],"Body-Biasing":[45],"(ABB)":[46],"circuit":[47,69,100],"therefore":[49],"needed":[50],"and":[51,87,96,154],"must":[52],"meet":[53],"ULP":[55],"constraints.":[56],"To":[57],"address":[58],"challenge,":[60],"programmable":[62],"negative":[63],"sampling":[64,78],"solution":[65,120,130],"optimized":[66],"ABB":[68,136],"in":[70,176],"18":[71],"nm":[72],"FD-SOI":[73],"proposed.":[76],"The":[77,99],"rate":[79],"ranges":[80],"from":[81],"10":[82,152],"kHz":[83,153],"100":[85],"MHz":[86],"introduces":[88],"specific":[89],"design":[90,169],"techniques":[91],"enhance":[93],"consumption":[95],"area":[97,157],"efficiency.":[98],"composed":[102],"modified":[105],"6-bit":[106],"binaryweighted":[107],"Capacitive":[108],"Digital":[109],"Analog":[111],"Converter":[112],"(CDAC)":[113],"coupled":[114],"with":[115],"dynamic":[117,123],"comparator.":[118],"This":[119,138],"exhibits":[121],"only":[122],"consumption,":[125],"it":[127],"suitable":[129],"frequency":[132],"regulation":[133],"circuit.":[137],"implementation":[139],"can":[140],"achieve":[141],"reduction":[144,158],"up":[145],"<tex":[147,160],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[148,161],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$\\times":[149],"460$</tex>":[150],"at":[151],"silicon":[156],"by":[159],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$x":[162],"7.5$</tex>":[163],"compared":[164],"previously":[167],"implemented":[168],"that":[170],"relies":[171],"statically":[173],"biased":[174],"functions":[175],"same":[178],"technology.":[179]},"counts_by_year":[],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2025-12-11T00:00:00"}