{"id":"https://openalex.org/W4389544798","doi":"https://doi.org/10.1109/dcis58620.2023.10335964","title":"Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks","display_name":"Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural Networks","publication_year":2023,"publication_date":"2023-11-15","ids":{"openalex":"https://openalex.org/W4389544798","doi":"https://doi.org/10.1109/dcis58620.2023.10335964"},"language":"en","primary_location":{"id":"doi:10.1109/dcis58620.2023.10335964","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis58620.2023.10335964","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073065353","display_name":"Samuel L\u00f3pez-Asunci\u00f3n","orcid":"https://orcid.org/0000-0002-3186-1415"},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Samuel L\u00f3pez-Asunci\u00f3n","raw_affiliation_strings":["Universidad Politécnica de Madrid,Integrated Systems Laboratory (LSI),Madrid,Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Politécnica de Madrid,Integrated Systems Laboratory (LSI),Madrid,Spain","institution_ids":["https://openalex.org/I88060688"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103369591","display_name":"Pablo Ituero Herrero","orcid":null},"institutions":[{"id":"https://openalex.org/I88060688","display_name":"Universidad Polit\u00e9cnica de Madrid","ror":"https://ror.org/03n6nwv02","country_code":"ES","type":"education","lineage":["https://openalex.org/I88060688"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pablo Ituero Herrero","raw_affiliation_strings":["Universidad Politécnica de Madrid,Integrated Systems Laboratory (LSI),Madrid,Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidad Politécnica de Madrid,Integrated Systems Laboratory (LSI),Madrid,Spain","institution_ids":["https://openalex.org/I88060688"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I88060688"],"apc_list":null,"apc_paid":null,"fwci":0.5409,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.59982024,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10581","display_name":"Neural dynamics and brain function","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2805","display_name":"Cognitive Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8415783643722534},{"id":"https://openalex.org/keywords/spiking-neural-network","display_name":"Spiking neural network","score":0.8404263257980347},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7433008551597595},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.5966819524765015},{"id":"https://openalex.org/keywords/biological-neuron-model","display_name":"Biological neuron model","score":0.47862380743026733},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46295174956321716},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.44087591767311096},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3866451680660248},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36653438210487366},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.303407222032547}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8415783643722534},{"id":"https://openalex.org/C11731999","wikidata":"https://www.wikidata.org/wiki/Q9067355","display_name":"Spiking neural network","level":3,"score":0.8404263257980347},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7433008551597595},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.5966819524765015},{"id":"https://openalex.org/C186565885","wikidata":"https://www.wikidata.org/wiki/Q1651163","display_name":"Biological neuron model","level":3,"score":0.47862380743026733},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46295174956321716},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.44087591767311096},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3866451680660248},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36653438210487366},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.303407222032547},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dcis58620.2023.10335964","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis58620.2023.10335964","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1836836553","https://openalex.org/W1984374486","https://openalex.org/W2006370340","https://openalex.org/W2043679829","https://openalex.org/W2088192327","https://openalex.org/W2140886546","https://openalex.org/W2153041354","https://openalex.org/W2528596247","https://openalex.org/W2571808120","https://openalex.org/W2783525259","https://openalex.org/W2888850715","https://openalex.org/W2966081953","https://openalex.org/W3102313165","https://openalex.org/W3115631645","https://openalex.org/W3129730378","https://openalex.org/W3160942557","https://openalex.org/W3169504881","https://openalex.org/W3208637127","https://openalex.org/W4226443758","https://openalex.org/W4283749998","https://openalex.org/W4298000286","https://openalex.org/W4312044827","https://openalex.org/W6796725052"],"related_works":["https://openalex.org/W2023492997","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W2013860114","https://openalex.org/W1608572506","https://openalex.org/W2403181385","https://openalex.org/W4213353724","https://openalex.org/W1504796302","https://openalex.org/W2906832317","https://openalex.org/W2996874253"],"abstract_inverted_index":{"Spiking":[0],"neural":[1,13],"networks":[2,14],"(SNNs)":[3],"promise":[4],"to":[5,37,63,100,135],"perform":[6],"tasks":[7],"currently":[8],"done":[9],"by":[10],"classical":[11],"artificial":[12],"(ANNs)":[15],"faster,":[16],"in":[17,47],"smaller":[18],"footprints":[19],"and":[20,51,65,75,114,128],"using":[21],"less":[22,137],"energy.":[23],"To":[24],"gain":[25],"more":[26],"insight":[27],"into":[28],"these":[29,42],"new":[30],"information":[31],"processing":[32,93],"architectures,":[33],"researchers":[34],"need":[35,58],"tools":[36],"simulate":[38,101],"their":[39,72],"networks.":[40],"However,":[41],"structures":[43],"can":[44],"be":[45],"challenging":[46],"terms":[48],"of":[49,103,111,121],"complexity":[50],"size,":[52],"so":[53],"there":[54],"is":[55,78,97,133],"an":[56],"increasing":[57],"for":[59,82],"acceleration.":[60],"In":[61],"contrast":[62],"CPU":[64],"GPU-based":[66],"systems,":[67],"FPGAs":[68],"are":[69],"ideal":[70],"as":[71],"distributed":[73,116],"architecture":[74],"parallel":[76],"nature":[77],"very":[79],"well":[80],"suited":[81],"spiking":[83,91],"neuron":[84,92,107,132,140],"implementation.This":[85],"work":[86],"proposes":[87],"a":[88,118],"clock-driven":[89],"FPGA-based":[90],"core":[94,123],"architecture,":[95],"which":[96],"flexible":[98],"enough":[99],"groups":[102],"neurons":[104,127],"with":[105,124],"arbitrary":[106],"models.":[108],"Taking":[109],"advantage":[110],"deep":[112],"pipelining":[113],"fast":[115],"memory,":[117],"particular":[119],"implementation":[120],"this":[122],"2048":[125],"Leaky-Integrate-and-Fire":[126],"128":[129],"synapses":[130],"per":[131,139],"able":[134],"use":[136],"area":[138],"than":[141],"current":[142],"state-of-the-art":[143],"implementations":[144],"while":[145],"also":[146],"reaching":[147],"low":[148],"simulation":[149],"step":[150],"times.":[151]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}