{"id":"https://openalex.org/W4206210640","doi":"https://doi.org/10.1109/dcis53048.2021.9666182","title":"Iterative Method for Performance Prediction Improvement of Integrated Circuits","display_name":"Iterative Method for Performance Prediction Improvement of Integrated Circuits","publication_year":2021,"publication_date":"2021-11-24","ids":{"openalex":"https://openalex.org/W4206210640","doi":"https://doi.org/10.1109/dcis53048.2021.9666182"},"language":"en","primary_location":{"id":"doi:10.1109/dcis53048.2021.9666182","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis53048.2021.9666182","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-03710383","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007007822","display_name":"Gwenael Chaillou","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4412460525"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Gwenael Chaillou","raw_affiliation_strings":["LIRMM, Univ. of Montpellier, CNRS, Montpellier, France"],"affiliations":[{"raw_affiliation_string":"LIRMM, Univ. of Montpellier, CNRS, Montpellier, France","institution_ids":["https://openalex.org/I4210101743","https://openalex.org/I19894307","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015351510","display_name":"Philippe Maurine","orcid":"https://orcid.org/0000-0002-9706-5710"},"institutions":[{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4412460525"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Philippe Maurine","raw_affiliation_strings":["LIRMM, Univ. of Montpellier, CNRS, Montpellier, France"],"affiliations":[{"raw_affiliation_string":"LIRMM, Univ. of Montpellier, CNRS, Montpellier, France","institution_ids":["https://openalex.org/I4210101743","https://openalex.org/I19894307","https://openalex.org/I1294671590"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109071973","display_name":"Jean-Marc Galli\u00e8re","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4412460525"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Jean-Marc Galliere","raw_affiliation_strings":["LIRMM, Univ. of Montpellier, CNRS, Montpellier, France"],"affiliations":[{"raw_affiliation_string":"LIRMM, Univ. of Montpellier, CNRS, Montpellier, France","institution_ids":["https://openalex.org/I4210101743","https://openalex.org/I19894307","https://openalex.org/I1294671590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108376202","display_name":"Nadine Az\u00e9mard","orcid":null},"institutions":[{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4412460525"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Nadine Azemard","raw_affiliation_strings":["LIRMM, Univ. of Montpellier, CNRS, Montpellier, France"],"affiliations":[{"raw_affiliation_string":"LIRMM, Univ. of Montpellier, CNRS, Montpellier, France","institution_ids":["https://openalex.org/I4210101743","https://openalex.org/I19894307","https://openalex.org/I1294671590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5007007822"],"corresponding_institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I19894307","https://openalex.org/I4210101743"],"apc_list":null,"apc_paid":null,"fwci":0.1003,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.4622612,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7060673236846924},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6306657791137695},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6281127333641052},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6221782565116882},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5663389563560486},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5557330846786499},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.4781033396720886},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.46797114610671997},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45802199840545654},{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.45237621665000916},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.44350650906562805},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4251217842102051},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.42054009437561035},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3656451404094696},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.36253821849823},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.35695981979370117},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2837753891944885},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24270012974739075},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18413713574409485},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16015169024467468}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7060673236846924},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6306657791137695},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6281127333641052},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6221782565116882},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5663389563560486},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5557330846786499},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.4781033396720886},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.46797114610671997},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45802199840545654},{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.45237621665000916},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.44350650906562805},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4251217842102051},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.42054009437561035},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3656451404094696},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.36253821849823},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.35695981979370117},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2837753891944885},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24270012974739075},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18413713574409485},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16015169024467468},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dcis53048.2021.9666182","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis53048.2021.9666182","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:lirmm-03710383v1","is_oa":true,"landing_page_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-03710383","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DCIS 2021 - 36th Conference on Design of Circuits and Integrated Systems, Nov 2021, Vila do Conde, Portugal. pp.1-5, ⟨10.1109/DCIS53048.2021.9666182⟩","raw_type":"Conference papers"}],"best_oa_location":{"id":"pmh:oai:HAL:lirmm-03710383v1","is_oa":true,"landing_page_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-03710383","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DCIS 2021 - 36th Conference on Design of Circuits and Integrated Systems, Nov 2021, Vila do Conde, Portugal. pp.1-5, ⟨10.1109/DCIS53048.2021.9666182⟩","raw_type":"Conference papers"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7400000095367432}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2107916809","https://openalex.org/W2165190641","https://openalex.org/W4240067961"],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W2743305891","https://openalex.org/W2908947570","https://openalex.org/W2070693700","https://openalex.org/W2151657833","https://openalex.org/W2156138647","https://openalex.org/W1617216077","https://openalex.org/W1987597317","https://openalex.org/W2097839191"],"abstract_inverted_index":{"Currently,":[0],"the":[1,10,28,33,36,42,51,55,58,69,74,84,90,101,105,115,138,148,151],"design":[2,29,103],"flow":[3,30],"of":[4,12,19,27,35,44,48,57,68,73,86,107,114,131,150],"digital":[5],"integrated":[6],"circuits":[7,91],"relies":[8],"on":[9,127],"use":[11,106,130],"pre-characterized":[13],"libraries.":[14],"These":[15],"libraries,":[16],"pre-calculated":[17],"outside":[18],"any":[20],"context,":[21],"are":[22,39],"used":[23],"at":[24],"each":[25],"step":[26],"to":[31,111,136,145],"predict":[32,147],"performance":[34],"circuit.":[37],"They":[38],"necessary":[40],"for":[41],"calculation":[43],"a":[45,128],"wide":[46],"variety":[47],"characteristics,":[49],"including":[50],"IR":[52,139],"Drop.":[53],"However,":[54],"behavior":[56],"logic":[59,87],"gates":[60,88],"described":[61],"in":[62,89],"these":[63,108],"libraries":[64,109,133],"is":[65,79],"not":[66],"representative":[67],"real":[70],"power":[71],"supply":[72],"standard-cells":[75],"and":[76,143],"this":[77,94],"difference":[78],"even":[80],"more":[81,141],"important":[82],"as":[83],"number":[85],"increases.":[92],"In":[93],"paper,":[95],"we":[96,121],"will":[97],"show":[98],"that":[99,134],"with":[100],"current":[102],"flow,":[104],"leads":[110],"an":[112,123],"underestimation":[113],"circuit":[116],"performances.":[117],"To":[118],"remedy":[119],"this,":[120],"propose":[122],"iterative":[124],"approach":[125],"based":[126],"new":[129],"voltage-adaptive":[132],"allows":[135],"compute":[137],"Drop":[140],"precisely":[142],"thus":[144],"better":[146],"performances":[149],"circuits.":[152]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}