{"id":"https://openalex.org/W3107467316","doi":"https://doi.org/10.1109/dcis51330.2020.9268638","title":"Hardware architecture for integrate-and-fire signal reconstruction on FPGA","display_name":"Hardware architecture for integrate-and-fire signal reconstruction on FPGA","publication_year":2020,"publication_date":"2020-11-18","ids":{"openalex":"https://openalex.org/W3107467316","doi":"https://doi.org/10.1109/dcis51330.2020.9268638","mag":"3107467316"},"language":"en","primary_location":{"id":"doi:10.1109/dcis51330.2020.9268638","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis51330.2020.9268638","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040008614","display_name":"Guilherme Carvalho","orcid":"https://orcid.org/0000-0003-3918-8955"},"institutions":[{"id":"https://openalex.org/I4210125590","display_name":"Institute for Systems Engineering and Computers","ror":"https://ror.org/033wn8m60","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I182534213","display_name":"Universidade do Porto","ror":"https://ror.org/043pwc612","country_code":"PT","type":"education","lineage":["https://openalex.org/I182534213"]},{"id":"https://openalex.org/I4210166615","display_name":"INESC TEC","ror":"https://ror.org/05fa8ka61","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I4210125590","https://openalex.org/I4210166615"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"Guilherme Carvalho","raw_affiliation_strings":["Instituto de Engenharia de Sistemas e Computadores - Tecnologia e Ci\u00eancia (INESC-TEC), Faculdade de Engenharia da Universidade do Porto (FEUP), Porto, Portugal"],"affiliations":[{"raw_affiliation_string":"Instituto de Engenharia de Sistemas e Computadores - Tecnologia e Ci\u00eancia (INESC-TEC), Faculdade de Engenharia da Universidade do Porto (FEUP), Porto, Portugal","institution_ids":["https://openalex.org/I4210125590","https://openalex.org/I182534213","https://openalex.org/I4210166615"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107062770","display_name":"Jo\u00e3o Canas Ferreira","orcid":"https://orcid.org/0000-0001-7471-3888"},"institutions":[{"id":"https://openalex.org/I4210125590","display_name":"Institute for Systems Engineering and Computers","ror":"https://ror.org/033wn8m60","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I4210166615","display_name":"INESC TEC","ror":"https://ror.org/05fa8ka61","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I4210125590","https://openalex.org/I4210166615"]},{"id":"https://openalex.org/I182534213","display_name":"Universidade do Porto","ror":"https://ror.org/043pwc612","country_code":"PT","type":"education","lineage":["https://openalex.org/I182534213"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Joao Canas Ferreira","raw_affiliation_strings":["Instituto de Engenharia de Sistemas e Computadores - Tecnologia e Ci\u00eancia (INESC-TEC), Faculdade de Engenharia da Universidade do Porto (FEUP), Porto, Portugal"],"affiliations":[{"raw_affiliation_string":"Instituto de Engenharia de Sistemas e Computadores - Tecnologia e Ci\u00eancia (INESC-TEC), Faculdade de Engenharia da Universidade do Porto (FEUP), Porto, Portugal","institution_ids":["https://openalex.org/I4210125590","https://openalex.org/I182534213","https://openalex.org/I4210166615"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112025019","display_name":"V\u00edtor Grade Tavares","orcid":"https://orcid.org/0000-0001-9646-7040"},"institutions":[{"id":"https://openalex.org/I4210125590","display_name":"Institute for Systems Engineering and Computers","ror":"https://ror.org/033wn8m60","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I4210166615","display_name":"INESC TEC","ror":"https://ror.org/05fa8ka61","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I4210125590","https://openalex.org/I4210166615"]},{"id":"https://openalex.org/I182534213","display_name":"Universidade do Porto","ror":"https://ror.org/043pwc612","country_code":"PT","type":"education","lineage":["https://openalex.org/I182534213"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Vitor Grade Tavares","raw_affiliation_strings":["Instituto de Engenharia de Sistemas e Computadores - Tecnologia e Ci\u00eancia (INESC-TEC), Faculdade de Engenharia da Universidade do Porto (FEUP), Porto, Portugal"],"affiliations":[{"raw_affiliation_string":"Instituto de Engenharia de Sistemas e Computadores - Tecnologia e Ci\u00eancia (INESC-TEC), Faculdade de Engenharia da Universidade do Porto (FEUP), Porto, Portugal","institution_ids":["https://openalex.org/I4210125590","https://openalex.org/I182534213","https://openalex.org/I4210166615"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5040008614"],"corresponding_institution_ids":["https://openalex.org/I182534213","https://openalex.org/I4210125590","https://openalex.org/I4210166615"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.11748667,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7274705171585083},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7166781425476074},{"id":"https://openalex.org/keywords/effective-number-of-bits","display_name":"Effective number of bits","score":0.7056626081466675},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.62392258644104},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.6042764782905579},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.5046573877334595},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4888107478618622},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.4768608510494232},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45950978994369507},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3796330690383911},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.27426236867904663},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14287933707237244},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.12182271480560303},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10592254996299744},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.09142449498176575}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7274705171585083},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7166781425476074},{"id":"https://openalex.org/C16671190","wikidata":"https://www.wikidata.org/wiki/Q505579","display_name":"Effective number of bits","level":3,"score":0.7056626081466675},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.62392258644104},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.6042764782905579},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.5046573877334595},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4888107478618622},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4768608510494232},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45950978994369507},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3796330690383911},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.27426236867904663},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14287933707237244},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.12182271480560303},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10592254996299744},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.09142449498176575},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dcis51330.2020.9268638","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis51330.2020.9268638","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.800000011920929,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W192379684","https://openalex.org/W1482223596","https://openalex.org/W1526826569","https://openalex.org/W1974511160","https://openalex.org/W1985940938","https://openalex.org/W1999483147","https://openalex.org/W2016227125","https://openalex.org/W2020122583","https://openalex.org/W2021810545","https://openalex.org/W2051630748","https://openalex.org/W2083531892","https://openalex.org/W2108906360","https://openalex.org/W2114554684","https://openalex.org/W2134007722","https://openalex.org/W2149288007","https://openalex.org/W2159035702","https://openalex.org/W2162800060","https://openalex.org/W2162894511","https://openalex.org/W2165107283","https://openalex.org/W2170779872","https://openalex.org/W2320578393","https://openalex.org/W2412148820","https://openalex.org/W3103759548","https://openalex.org/W4285719527","https://openalex.org/W6607961038","https://openalex.org/W6663565036","https://openalex.org/W6676387448","https://openalex.org/W6677182369","https://openalex.org/W6679703066"],"related_works":["https://openalex.org/W2368824897","https://openalex.org/W2364622490","https://openalex.org/W1508050556","https://openalex.org/W1910862367","https://openalex.org/W4301373716","https://openalex.org/W1950940422","https://openalex.org/W2379365082","https://openalex.org/W2370747590","https://openalex.org/W4283822356","https://openalex.org/W2030109976"],"abstract_inverted_index":{"Typical":[0],"analogue-to-digital":[1],"conversion":[2],"(ADC)":[3],"architectures,":[4],"at":[5],"Nyquist":[6],"rate,":[7],"tend":[8],"to":[9,21,76,87],"occupy":[10],"a":[11,36,56,83,94,107,120,128,142],"big":[12],"portion":[13],"of":[14,31,61,73,111,135],"the":[15,29,77,97,117,126,133,136],"integrated":[16],"circuit":[17],"die":[18],"area":[19,46],"and":[20,47,67,114,152],"consume":[22],"more":[23,88],"power":[24,48,122],"than":[25],"desired.":[26],"Recently,":[27],"with":[28,85],"rise":[30],"Interet-of-Things":[32],"(IoT),":[33],"there":[34],"is":[35,104,150],"high":[37,160],"demand":[38],"for":[39,132],"architectures":[40],"that":[41],"can":[42],"have":[43],"both":[44],"reduced":[45],"consumption.":[49],"Time":[50],"encoding":[51],"machines":[52],"(TEM)":[53],"might":[54],"be":[55,146],"promising":[57],"alternative.":[58],"These":[59],"types":[60],"encoders":[62],"result":[63],"in":[64,82,119],"very":[65,121],"simple":[66],"low-power":[68],"analogue":[69],"circuits,":[70],"shifting":[71],"most":[72],"its":[74],"complexity":[75],"decoding":[78],"stage,":[79],"typically":[80],"stationed":[81],"place":[84],"access":[86],"resources.":[89],"This":[90],"paper":[91],"focuses":[92],"on":[93,106,141,154],"particular":[95],"TEM,":[96],"integrate-and-fire":[98],"neuron":[99],"(IFN).":[100],"The":[101,148],"IFN":[102,137],"modulation":[103],"based":[105,140],"simplified":[108],"first-order":[109],"model":[110,144],"neural":[112],"operation":[113],"it":[115],"encodes":[116],"signal":[118,139],"efficient":[123],"manner.":[124],"In":[125],"end,":[127],"novel":[129],"hardware":[130],"architecture":[131],"reconstruction":[134],"encoded":[138],"spiking":[143],"will":[145],"presented.":[147],"method":[149],"demonstrated":[151],"implemented":[153],"FPGA,":[155],"reaching":[156],"an":[157],"ENOB":[158],"as":[159,161],"8.23.":[162]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}