{"id":"https://openalex.org/W3107000006","doi":"https://doi.org/10.1109/dcis51330.2020.9268616","title":"Evaluation of Software Inter-Processor Synchronization Methods for the Zynq-UltraScale+ Architecture","display_name":"Evaluation of Software Inter-Processor Synchronization Methods for the Zynq-UltraScale+ Architecture","publication_year":2020,"publication_date":"2020-11-18","ids":{"openalex":"https://openalex.org/W3107000006","doi":"https://doi.org/10.1109/dcis51330.2020.9268616","mag":"3107000006"},"language":"en","primary_location":{"id":"doi:10.1109/dcis51330.2020.9268616","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis51330.2020.9268616","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016818614","display_name":"Rub\u00e9n Nieto","orcid":"https://orcid.org/0000-0002-8293-9665"},"institutions":[{"id":"https://openalex.org/I189268942","display_name":"Universidad de Alcal\u00e1","ror":"https://ror.org/04pmn0e78","country_code":"ES","type":"education","lineage":["https://openalex.org/I189268942"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Ruben Nieto","raw_affiliation_strings":["University of Alcal\u00e1, Alcal\u00e1 de Henares (Madrid), Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Alcal\u00e1, Alcal\u00e1 de Henares (Madrid), Spain","institution_ids":["https://openalex.org/I189268942"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003464244","display_name":"E. Diaz","orcid":"https://orcid.org/0000-0003-0005-6517"},"institutions":[{"id":"https://openalex.org/I189268942","display_name":"Universidad de Alcal\u00e1","ror":"https://ror.org/04pmn0e78","country_code":"ES","type":"education","lineage":["https://openalex.org/I189268942"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Edel Diaz","raw_affiliation_strings":["University of Alcal\u00e1, Alcal\u00e1 de Henares (Madrid), Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Alcal\u00e1, Alcal\u00e1 de Henares (Madrid), Spain","institution_ids":["https://openalex.org/I189268942"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006489484","display_name":"R. Mateos","orcid":"https://orcid.org/0000-0002-1133-7165"},"institutions":[{"id":"https://openalex.org/I189268942","display_name":"Universidad de Alcal\u00e1","ror":"https://ror.org/04pmn0e78","country_code":"ES","type":"education","lineage":["https://openalex.org/I189268942"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Raul Mateos","raw_affiliation_strings":["University of Alcal\u00e1, Alcal\u00e1 de Henares (Madrid), Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Alcal\u00e1, Alcal\u00e1 de Henares (Madrid), Spain","institution_ids":["https://openalex.org/I189268942"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063313091","display_name":"\u00c1lvaro Hern\u00e1ndez","orcid":"https://orcid.org/0000-0001-9308-8133"},"institutions":[{"id":"https://openalex.org/I189268942","display_name":"Universidad de Alcal\u00e1","ror":"https://ror.org/04pmn0e78","country_code":"ES","type":"education","lineage":["https://openalex.org/I189268942"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Alvaro Hernandez","raw_affiliation_strings":["University of Alcal\u00e1, Alcal\u00e1 de Henares (Madrid), Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Alcal\u00e1, Alcal\u00e1 de Henares (Madrid), Spain","institution_ids":["https://openalex.org/I189268942"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.236,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.52120017,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.9168687462806702},{"id":"https://openalex.org/keywords/interrupt","display_name":"Interrupt","score":0.828160285949707},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8042523860931396},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.7955332398414612},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.660914421081543},{"id":"https://openalex.org/keywords/semaphore","display_name":"Semaphore","score":0.6606871485710144},{"id":"https://openalex.org/keywords/arm-architecture","display_name":"ARM architecture","score":0.619475781917572},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5822792649269104},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.49413469433784485},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.4508473873138428},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.441169798374176},{"id":"https://openalex.org/keywords/graphics-processing-unit","display_name":"Graphics processing unit","score":0.41841748356819153},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3812609612941742},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3375700116157532},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.14438596367835999},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.10184833407402039},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.0758892297744751}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.9168687462806702},{"id":"https://openalex.org/C41661131","wikidata":"https://www.wikidata.org/wiki/Q220764","display_name":"Interrupt","level":3,"score":0.828160285949707},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8042523860931396},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.7955332398414612},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.660914421081543},{"id":"https://openalex.org/C95203288","wikidata":"https://www.wikidata.org/wiki/Q221682","display_name":"Semaphore","level":2,"score":0.6606871485710144},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.619475781917572},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5822792649269104},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.49413469433784485},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.4508473873138428},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.441169798374176},{"id":"https://openalex.org/C2779851693","wikidata":"https://www.wikidata.org/wiki/Q183484","display_name":"Graphics processing unit","level":2,"score":0.41841748356819153},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3812609612941742},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3375700116157532},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.14438596367835999},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.10184833407402039},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0758892297744751}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dcis51330.2020.9268616","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis51330.2020.9268616","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7900000214576721,"id":"https://metadata.un.org/sdg/10","display_name":"Reduced inequalities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1967926918","https://openalex.org/W1996916491","https://openalex.org/W2033872646","https://openalex.org/W2134669304","https://openalex.org/W2167619566","https://openalex.org/W2605479516","https://openalex.org/W2786971077","https://openalex.org/W2913750922","https://openalex.org/W2978177067","https://openalex.org/W3004147568","https://openalex.org/W4229954529","https://openalex.org/W4254858708"],"related_works":["https://openalex.org/W2314057185","https://openalex.org/W4241364390","https://openalex.org/W2322202043","https://openalex.org/W2350504666","https://openalex.org/W2012277354","https://openalex.org/W4381416760","https://openalex.org/W2087544673","https://openalex.org/W2368664215","https://openalex.org/W2382264333","https://openalex.org/W2371350567"],"abstract_inverted_index":{"Current":[0],"embedded":[1],"systems":[2],"provide":[3],"diverse":[4],"functionalities":[5],"and":[6,132,152],"their":[7],"features":[8],"are":[9,106,139],"evolving":[10],"constantly.":[11],"This":[12],"is":[13,24,69,111,124],"the":[14,17,59,63,95,99,117,122,127,142,147,154,174,183],"case":[15],"of":[16,92,98,109,129,144,169,177],"Zynq-UltraScale+":[18],"(US+)":[19],"MPSoC":[20,104],"family,":[21],"where":[22],"it":[23],"possible":[25],"to":[26,40,164],"find":[27],"a":[28,73,102,179,187],"System-on-Chip":[29],"(SoC)":[30],"architecture":[31],"with":[32],"an":[33,83],"Application":[34],"Processor":[35,50,55],"Unit":[36],"(APU)":[37],"containing":[38],"up":[39],"four":[41,96],"Cortex":[42],"A53":[43],"processing":[44],"units,":[45],"as":[46,48],"well":[47],"Graphics":[49],"Units":[51,56],"(GPUs)":[52],"or":[53,186],"Real-Time":[54],"(RPUs)":[57],"in":[58,77,79,101,167],"same":[60],"device.":[61],"Nevertheless,":[62],"synchronization":[64,93,181,189],"among":[65,94,182,190],"these":[66],"different":[67,184],"units":[68],"crucial":[70],"whether":[71],"tackling":[72],"multi-core":[74],"approach,":[75],"especially":[76],"applications":[78],"standalone":[80],"mode,":[81],"without":[82],"Operating":[84],"System":[85],"(OS).":[86],"In":[87],"this":[88],"work,":[89],"two":[90],"methods":[91,138],"cores":[97,185],"APU":[100],"Zynq-US+":[103],"device":[105],"presented.":[107],"One":[108],"them":[110],"based":[112,125],"on":[113,126],"sending":[114],"interrupts":[115],"using":[116],"InterProcessor":[118],"Interrupt":[119],"(IPI),":[120],"whereas":[121],"other":[123],"use":[128],"atomic":[130],"instructions":[131],"mutual":[133],"exclusion":[134],"variables":[135],"(mutex).":[136],"Both":[137],"managed":[140],"by":[141,151],"exchange":[143],"messages":[145],"between":[146],"processors,":[148],"previously":[149],"defined":[150],"for":[153],"application.":[155],"The":[156],"experimental":[157],"results":[158],"presented":[159],"here":[160],"allow":[161],"both":[162],"proposals":[163],"be":[165],"compared":[166],"terms":[168],"running":[170],"times,":[171],"also":[172],"considering":[173],"particular":[175],"cases":[176],"either":[178],"cascaded":[180],"broadcast":[188],"processors.":[191]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}