{"id":"https://openalex.org/W2999162532","doi":"https://doi.org/10.1109/dcis201949030.2019.8959871","title":"Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities","display_name":"Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities","publication_year":2019,"publication_date":"2019-11-01","ids":{"openalex":"https://openalex.org/W2999162532","doi":"https://doi.org/10.1109/dcis201949030.2019.8959871","mag":"2999162532"},"language":"en","primary_location":{"id":"doi:10.1109/dcis201949030.2019.8959871","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis201949030.2019.8959871","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://ruc.udc.es/dspace/bitstream/2183/27369/2/R.R.Osorio_Hardware_Implementation_of_Statecharts_for_FPGA-based.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074664866","display_name":"Javier Cereijo Garc\u00eda","orcid":"https://orcid.org/0000-0003-0175-179X"},"institutions":[{"id":"https://openalex.org/I2799828880","display_name":"European Spallation Source","ror":"https://ror.org/01wv9cn34","country_code":"SE","type":"facility","lineage":["https://openalex.org/I2799828880"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Javier Cereijo Garcia","raw_affiliation_strings":["European Spallation Source, Lund, Sweden"],"affiliations":[{"raw_affiliation_string":"European Spallation Source, Lund, Sweden","institution_ids":["https://openalex.org/I2799828880"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032890813","display_name":"Roberto R. Osorio","orcid":"https://orcid.org/0000-0001-8768-2240"},"institutions":[{"id":"https://openalex.org/I11019714","display_name":"Universidade da Coru\u00f1a","ror":"https://ror.org/01qckj285","country_code":"ES","type":"education","lineage":["https://openalex.org/I11019714"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Roberto R. Osorio","raw_affiliation_strings":["Dept. Computer Engineering, University of A Coru\u00f1a, CITIC, A Coru\u00f1a, Spain"],"affiliations":[{"raw_affiliation_string":"Dept. Computer Engineering, University of A Coru\u00f1a, CITIC, A Coru\u00f1a, Spain","institution_ids":["https://openalex.org/I11019714"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074664866"],"corresponding_institution_ids":["https://openalex.org/I2799828880"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.2193126,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8356423377990723},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.745769739151001},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6789036989212036},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5584880709648132},{"id":"https://openalex.org/keywords/variety","display_name":"Variety (cybernetics)","score":0.5106642842292786},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.49283623695373535},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.49154338240623474},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.4848855435848236},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.45318859815597534},{"id":"https://openalex.org/keywords/control","display_name":"Control (management)","score":0.4123286306858063},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3547401428222656},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.24853667616844177},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.1162506639957428}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8356423377990723},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.745769739151001},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6789036989212036},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5584880709648132},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.5106642842292786},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.49283623695373535},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.49154338240623474},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.4848855435848236},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.45318859815597534},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.4123286306858063},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3547401428222656},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.24853667616844177},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.1162506639957428},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/dcis201949030.2019.8959871","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis201949030.2019.8959871","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},{"id":"pmh:oai:ruc.udc.es:2183/27369","is_oa":true,"landing_page_url":"http://hdl.handle.net/2183/27369","pdf_url":"https://ruc.udc.es/dspace/bitstream/2183/27369/2/R.R.Osorio_Hardware_Implementation_of_Statecharts_for_FPGA-based.pdf","source":{"id":"https://openalex.org/S4306402204","display_name":"RUC (Universidade Da Coru\u00f1a)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:ruc.udc.es:2183/27369","is_oa":true,"landing_page_url":"http://hdl.handle.net/2183/27369","pdf_url":"https://ruc.udc.es/dspace/bitstream/2183/27369/2/R.R.Osorio_Hardware_Implementation_of_Statecharts_for_FPGA-based.pdf","source":{"id":"https://openalex.org/S4306402204","display_name":"RUC (Universidade Da Coru\u00f1a)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4000000059604645,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2999162532.pdf","grobid_xml":"https://content.openalex.org/works/W2999162532.grobid-xml"},"referenced_works_count":12,"referenced_works":["https://openalex.org/W1489500230","https://openalex.org/W1555192661","https://openalex.org/W2017959828","https://openalex.org/W2099529102","https://openalex.org/W2110236127","https://openalex.org/W2127380267","https://openalex.org/W2137237783","https://openalex.org/W2157253868","https://openalex.org/W2497118556","https://openalex.org/W4230274253","https://openalex.org/W4239370792","https://openalex.org/W4251033705"],"related_works":["https://openalex.org/W2121182846","https://openalex.org/W2155789024","https://openalex.org/W2315668284","https://openalex.org/W3213608175","https://openalex.org/W2109491806","https://openalex.org/W3117675750","https://openalex.org/W2141743053","https://openalex.org/W2037276323","https://openalex.org/W3095633856","https://openalex.org/W2058044441"],"abstract_inverted_index":{"The":[0],"problem":[1],"of":[2,23,36,50,86,155],"generating":[3],"complex":[4],"synchronization":[5,28],"patterns":[6],"using":[7,151],"automated":[8,112],"tools":[9,87],"is":[10,77,88,173],"addressed":[11],"in":[12,29,47,96,110],"this":[13,124],"paper.":[14],"This":[15],"work":[16,125],"was":[17],"originally":[18],"motivated":[19],"by":[20,75],"the":[21,44,56,68,93,120,147],"need":[22],"fast":[24],"and":[25,38,66,80,99,102,123,145,165],"jitter":[26],"free":[27],"scientific":[30],"facilities,":[31],"where":[32],"a":[33,48,78,84,97,138,142],"large":[34],"number":[35,154],"sensors":[37],"actuators":[39],"must":[40],"be":[41],"controlled":[42],"at":[43],"right":[45],"time":[46],"variety":[49],"situations.":[51],"Programmable":[52],"processors":[53],"cannot":[54],"meet":[55],"real-time":[57],"requirements,":[58],"forcing":[59],"to":[60,64,129,159],"use":[61],"dedicated":[62],"circuits":[63],"produce":[65],"transmit":[67],"control":[69,94,149],"signals.":[70],"Designing":[71],"application":[72],"specific":[73],"hardware":[74],"hand":[76],"slow":[79],"error-prone":[81],"task.":[82],"Hence,":[83],"set":[85],"required":[89,148],"that":[90,140],"allow":[91],"specifying":[92],"systems":[95,150],"clear":[98],"efficient":[100],"way":[101],"producing":[103],"synthesizable":[104],"HDL":[105,134],"(hardware":[106],"description":[107],"language)":[108],"code":[109],"an":[111,169],"manner.":[113],"Statechart":[114],"diagrams":[115,132],"have":[116],"been":[117],"selected":[118],"as":[119],"input":[121],"method,":[122],"focuses":[126],"on":[127],"how":[128],"translate":[130],"those":[131],"into":[133],"code.":[135],"We":[136],"present":[137],"tool":[139],"analyzes":[141],"Statecharts":[143],"specification":[144],"implements":[146],"FPGAs.":[152],"A":[153],"solutions":[156],"are":[157],"provided":[158],"deal":[160],"with":[161],"multiple":[162],"triggering":[163],"events":[164],"concurrent":[166],"super-states.":[167],"Also,":[168],"alternative":[170],"microprogrammed":[171],"implementation":[172],"proposed.":[174]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}