{"id":"https://openalex.org/W2940233160","doi":"https://doi.org/10.1109/dcis.2018.8681459","title":"Vector-Based Mismatch Shaping circuit for a low IF Multibit \u03a3\u2206 ADC","display_name":"Vector-Based Mismatch Shaping circuit for a low IF Multibit \u03a3\u2206 ADC","publication_year":2018,"publication_date":"2018-11-01","ids":{"openalex":"https://openalex.org/W2940233160","doi":"https://doi.org/10.1109/dcis.2018.8681459","mag":"2940233160"},"language":"en","primary_location":{"id":"doi:10.1109/dcis.2018.8681459","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis.2018.8681459","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030100022","display_name":"M. Portela-Garc\u00eda","orcid":"https://orcid.org/0000-0002-4103-0519"},"institutions":[{"id":"https://openalex.org/I50357001","display_name":"Universidad Carlos III de Madrid","ror":"https://ror.org/03ths8210","country_code":"ES","type":"education","lineage":["https://openalex.org/I50357001"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"M. Portela-Garcia","raw_affiliation_strings":["Electronics Technology Department, Carlos III University, Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Technology Department, Carlos III University, Madrid, Spain","institution_ids":["https://openalex.org/I50357001"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064023943","display_name":"V\u00edctor Medina","orcid":"https://orcid.org/0000-0002-1765-724X"},"institutions":[{"id":"https://openalex.org/I50357001","display_name":"Universidad Carlos III de Madrid","ror":"https://ror.org/03ths8210","country_code":"ES","type":"education","lineage":["https://openalex.org/I50357001"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"V. M. Medina","raw_affiliation_strings":["Electronics Technology Department, Carlos III University, Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Technology Department, Carlos III University, Madrid, Spain","institution_ids":["https://openalex.org/I50357001"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082932006","display_name":"Susana Pat\u00f3n","orcid":"https://orcid.org/0000-0003-0911-2642"},"institutions":[{"id":"https://openalex.org/I50357001","display_name":"Universidad Carlos III de Madrid","ror":"https://ror.org/03ths8210","country_code":"ES","type":"education","lineage":["https://openalex.org/I50357001"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"S. Paton","raw_affiliation_strings":["Electronics Technology Department, Carlos III University, Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Technology Department, Carlos III University, Madrid, Spain","institution_ids":["https://openalex.org/I50357001"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19336073,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5735139846801758},{"id":"https://openalex.org/keywords/band-pass-filter","display_name":"Band-pass filter","score":0.5430762767791748},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4919604957103729},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.4919569194316864},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4753023087978363},{"id":"https://openalex.org/keywords/center-frequency","display_name":"Center frequency","score":0.4526422619819641},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.4326225519180298},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.42653992772102356},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.30373162031173706},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21228116750717163},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.12184610962867737}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5735139846801758},{"id":"https://openalex.org/C147788027","wikidata":"https://www.wikidata.org/wiki/Q2718101","display_name":"Band-pass filter","level":2,"score":0.5430762767791748},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4919604957103729},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.4919569194316864},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4753023087978363},{"id":"https://openalex.org/C7054721","wikidata":"https://www.wikidata.org/wiki/Q1940572","display_name":"Center frequency","level":3,"score":0.4526422619819641},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.4326225519180298},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.42653992772102356},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.30373162031173706},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21228116750717163},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.12184610962867737},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dcis.2018.8681459","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dcis.2018.8681459","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 Conference on Design of Circuits and Integrated Systems (DCIS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.800000011920929}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1509148781","https://openalex.org/W1757777378","https://openalex.org/W1772165751","https://openalex.org/W2089914714","https://openalex.org/W2100884184","https://openalex.org/W2113662531","https://openalex.org/W2141449316","https://openalex.org/W2153299118","https://openalex.org/W2160579191","https://openalex.org/W2291681534","https://openalex.org/W2615846625","https://openalex.org/W2758790985"],"related_works":["https://openalex.org/W2072804028","https://openalex.org/W2044319823","https://openalex.org/W1965453741","https://openalex.org/W2164679691","https://openalex.org/W3023086838","https://openalex.org/W2102141309","https://openalex.org/W2113057816","https://openalex.org/W4312233850","https://openalex.org/W2352475234","https://openalex.org/W4200131216"],"abstract_inverted_index":{"This":[0],"paper":[1],"shows":[2],"the":[3,12,34,43,56,77,81,98,129],"design":[4,104],"of":[5,14,45],"a":[6,15,90],"mismatch":[7,86,101],"shaping":[8,87],"circuit":[9,88,123],"to":[10,53,72,80,96,132],"improve":[11],"linearity":[13],"multibit":[16],"bandpass":[17,100],"\u03a3\u2206":[18],"ADC":[19],"whose":[20],"center":[21],"frequency":[22],"is":[23,39,49,64],"f":[24],"<inf":[25],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[26],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">s</inf>":[27],"/32.":[28],"For":[29],"such":[30],"low":[31],"IF":[32],"ADC,":[33],"Data":[35,120],"Weighted":[36,121],"Averaging":[37,122],"algorithm":[38],"not":[40,50],"efficient":[41,66],"as":[42],"notch":[44,91],"shaped":[46],"quantization":[47],"noise":[48,74],"close":[51],"enough":[52],"DC.":[54],"On":[55],"other":[57],"hand,":[58],"an":[59],"N-path":[60],"transformation":[61],"using":[62],"N=32":[63],"only":[65],"for":[67],"very":[68],"narrow":[69],"bandwidths":[70],"due":[71],"increased":[73],"power":[75],"in":[76,108,112,128],"lobes":[78],"adjacent":[79],"targeted":[82],"notch.":[83],"A":[84,116],"vector-based":[85],"implementing":[89],"filter":[92],"has":[93,105,124],"been":[94,106,125],"designed":[95,127],"provide":[97],"desired":[99],"shaping.":[102],"The":[103],"described":[107],"VHDL":[109],"and":[110,135],"synthesized":[111],"180nm":[113],"CMOS":[114],"process.":[115],"switch":[117],"matrix":[118],"based":[119],"also":[126],"same":[130],"process":[131],"compare":[133],"speed":[134],"performance.":[136]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}