{"id":"https://openalex.org/W1979010479","doi":"https://doi.org/10.1109/dbta.2010.5658987","title":"Design of Image Data Compression IP Core Based on Processor Local Bus","display_name":"Design of Image Data Compression IP Core Based on Processor Local Bus","publication_year":2010,"publication_date":"2010-11-01","ids":{"openalex":"https://openalex.org/W1979010479","doi":"https://doi.org/10.1109/dbta.2010.5658987","mag":"1979010479"},"language":"en","primary_location":{"id":"doi:10.1109/dbta.2010.5658987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dbta.2010.5658987","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 2nd International Workshop on Database Technology and Applications","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100809578","display_name":"Xiaodong Xu","orcid":"https://orcid.org/0000-0003-0046-3964"},"institutions":[{"id":"https://openalex.org/I154099455","display_name":"Shandong University","ror":"https://ror.org/0207yh398","country_code":"CN","type":"education","lineage":["https://openalex.org/I154099455"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaodong Xu","raw_affiliation_strings":["Key Laboratory of High Efficiency and Clean Mechanical Manufacture, Ministry of Education, School of Mechanical Engineering, Shandong University, Jinan, China","Key Lab. of High-efficiency & Clean Mech. Manuf., Shandong Univ., Jinan, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of High Efficiency and Clean Mechanical Manufacture, Ministry of Education, School of Mechanical Engineering, Shandong University, Jinan, China","institution_ids":["https://openalex.org/I154099455"]},{"raw_affiliation_string":"Key Lab. of High-efficiency & Clean Mech. Manuf., Shandong Univ., Jinan, China","institution_ids":["https://openalex.org/I154099455"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101875730","display_name":"Yiqi Zhou","orcid":"https://orcid.org/0000-0003-3331-0251"},"institutions":[{"id":"https://openalex.org/I154099455","display_name":"Shandong University","ror":"https://ror.org/0207yh398","country_code":"CN","type":"education","lineage":["https://openalex.org/I154099455"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yiqi Zhou","raw_affiliation_strings":["Key Laboratory of High Efficiency and Clean Mechanical Manufacture, Ministry of Education, School of Mechanical Engineering, Shandong University, Jinan, China","Key Lab. of High-efficiency & Clean Mech. Manuf., Shandong Univ., Jinan, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of High Efficiency and Clean Mechanical Manufacture, Ministry of Education, School of Mechanical Engineering, Shandong University, Jinan, China","institution_ids":["https://openalex.org/I154099455"]},{"raw_affiliation_string":"Key Lab. of High-efficiency & Clean Mech. Manuf., Shandong Univ., Jinan, China","institution_ids":["https://openalex.org/I154099455"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I154099455"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"5","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13717","display_name":"Advanced Algorithms and Applications","score":0.9700999855995178,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9646000266075134,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modelsim","display_name":"ModelSim","score":0.760516881942749},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6565772294998169},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6527913212776184},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5911180973052979},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.5383857488632202},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5039364695549011},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4649127125740051},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.4596945345401764},{"id":"https://openalex.org/keywords/image-compression","display_name":"Image compression","score":0.45963746309280396},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.44566360116004944},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4387591481208801},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.4036143720149994},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.21761554479599},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.18182092905044556},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13586294651031494}],"concepts":[{"id":"https://openalex.org/C2778571676","wikidata":"https://www.wikidata.org/wiki/Q3317826","display_name":"ModelSim","level":4,"score":0.760516881942749},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6565772294998169},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6527913212776184},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5911180973052979},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.5383857488632202},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5039364695549011},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4649127125740051},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.4596945345401764},{"id":"https://openalex.org/C13481523","wikidata":"https://www.wikidata.org/wiki/Q412438","display_name":"Image compression","level":4,"score":0.45963746309280396},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.44566360116004944},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4387591481208801},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.4036143720149994},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.21761554479599},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.18182092905044556},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13586294651031494},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dbta.2010.5658987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dbta.2010.5658987","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 2nd International Workshop on Database Technology and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2018069368","https://openalex.org/W2089944071","https://openalex.org/W2112326120","https://openalex.org/W2135883010","https://openalex.org/W2142848556","https://openalex.org/W3143714452","https://openalex.org/W3144476955","https://openalex.org/W6654848894","https://openalex.org/W6680270260"],"related_works":["https://openalex.org/W2355127684","https://openalex.org/W2904030123","https://openalex.org/W2376722244","https://openalex.org/W4297665406","https://openalex.org/W2749962643","https://openalex.org/W2188510181","https://openalex.org/W2337621786","https://openalex.org/W2810194576","https://openalex.org/W2558178355","https://openalex.org/W2993673605"],"abstract_inverted_index":{"The":[0,22,59,94,117],"system":[1,124],"on":[2,8,51,64],"a":[3],"programmable":[4,18],"chip":[5],"(SoPC)":[6],"based":[7,50,63],"FPGA":[9],"has":[10],"some":[11],"special":[12],"characteristics,":[13],"such":[14],"as":[15],"flexibility,":[16],"customization,":[17],"hardware":[19],"and":[20,77,87,111,129,134],"software.":[21],"design":[23,36,43,95,132],"of":[24,37,44,54,97,104],"user":[25],"intellectual":[26],"property":[27],"(IP)":[28],"core":[29,49,61,90,119],"is":[30,62,91,100],"an":[31],"important":[32],"task":[33],"in":[34,121,136],"the":[35,42,52,83,102,108,114,122,127,131],"SoPC.":[38],"This":[39],"paper":[40],"presents":[41],"image":[45,66],"data":[46,67],"compression":[47,68],"IP":[48,60,89,118],"standard":[53,70],"processor":[55],"local":[56],"bus":[57],"(PLB).":[58],"CCSDS":[65],"\uff08IDC\uff09":[69],"which":[71],"includes":[72],"discrete":[73],"wavelet":[74],"transform":[75],"module":[76,99],"bit":[78],"plane":[79],"encoder":[80],"module.":[81],"Furthermore,":[82],"interface":[84],"between":[85],"PLB":[86],"IDC":[88],"also":[92],"designed.":[93],"program":[96],"each":[98],"using":[101],"language":[103],"VHDL,":[105],"simulated":[106],"by":[107,113],"software":[109,115],"modelsim,":[110],"realized":[112],"EDK.":[116],"designed":[120],"SoPC":[123],"greatly":[125],"speeds":[126],"encoding":[128],"makes":[130],"easier":[133],"stronger":[135],"expansibility.":[137]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}